Electronics > PCB/EDA/CAD

ModelSim simulation error: Failed to find matching specify module path


Hi I have written a very simple buffer circuit in verilog and a matching sdf file. I have added my sdf file in the start simulation window. but when i select my testbench file and start the simulation I get the following error:

vsim-SDF-3261: Failed to find matching specify module path

I am only using a single IOPATH delay in my sdf file.

Have any of you came across this error? what is the solution?

do you have spaces in path names ? that is a common reason for errors with modelsim et al..

Thanks for your reply,

I dont have any spaces in my paths. This is what I found to be the meaning of the error:

 # vsim Message # 3261:
> # No module path in a specify block in the related module instance was
> # found to match the SDF construct on the specified line. Verify that
> # the SDF file is being applied to the correct design instance and that
> # a specify block exists in this module instance and contains the
> # appropriate module path. If a COND is being used, verify that the order
> # of the condition is the same in the specify block as it is in the
> # SDF file.
> #

How can I include the appropiate module path in a specify block?

I found what I had to do. I had to write a specify verilog block in each of the modules that I instantiated.


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