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Options for via-in-pad on high current fets (for thermal control)

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For PCBs, what are the via-in-pad options for putting thermal via's in the middle of a D2PAK to get better thermal management? Obviously something is needed to avoid losing solder down the holes.

I know you can epoxy fill vias and plate over them, but afaik this is only for small via's and not the size you use for thermal management.

Does anyone know what options exist and what is the cheapest?
Is it best to put no holes in the pad and instead put them around the outside?

I need to pass around 40A through 1mR mosfet and it will probably be 2oz copper.
So 2W or so. However there will be lots of other mosfets on the same PCB
so i really want to pull the heat out of the mosfets into the middle pcb layers as much as humanly possible.

Previous threads

You can fill any via, the more important part is it's a laborious step so it's expensive and best avoided.

Use small vias, less prone to wicking solder (<= 0.3mm i.d.).  Plan for extra solder paste, and calculate how much would be left assuming all the vias fill up -- leave enough to give a small fillet on the tab.  The rest, fill in around with vias.  Do not tent the vias, leave them open both sides.

One or two watts is no problem for vias around the periphery.  More concerning is, if you have "lots" of FETs, you'll need to get a lot of heat out, period.  Consider clamping PCB to heatsink with thermal pad?



--- Quote from: T3sl4co1l on April 28, 2021, 08:35:10 am ---More concerning is, if you have "lots" of FETs, you'll need to get a lot of heat out, period.  Consider clamping PCB to heatsink with thermal pad?

--- End quote ---


Yes, the entire bottom of the PCB (130x120mm) will be attached to an aluminum plate with thermal adhesive tape.
The mosfets are all on the top layer so the critical thing is to get the heat out of the tiny mosfet package and spread it out over the PCB so the metal plate can do its thing.

Currently have ~16x 0.3mm via's for each mosfet's connection around the outside (none in pad)
PCB is 6 layer. The plan is 2oz outer layers and 4oz inner layers, but this will depend on pricing from pcb fab.
(Soldermask not shown in pic to make vias viewable)

Ah yeah, your high current motor driver thingy?

FYI to readers: if you're making another thread in a series, it helps to refer to your earlier threads for context, so we don't have to ask for clarification.  We don't all read every thread, or remember who all has posted them.  (Which, for my part, I'm poor at names... clearly I don't have much of an excuse in the other matter... :-DD )

Huh whats the device in the middle, it's not a MOSFET, all four pins are common.  Diode?  TVS?  Not aware of what's in PDSO-8, or LFPAK or whatever this is, that's a diode...

Can save a good, some mm's between the FETs and terminal blocks?

4oz inner is probably not the greatest.  You'll have to spend more clearance, including around vias -- may end up reducing cross section in critical areas.  The vias can be spread out to somewhat lower density to help with this.  Heat and current spreading on the top layers is paramount, and you may find 3oz is okay on that as well as meeting tolerances.  (You'll probably need to avoid TSSOP and such, but SOIC is fine.)

No bypass caps?  Or, everything on the bottom side?  I don't see gate resistors either... note by the way each transistor needs its own gate resistor, they can't be wired hard in parallel.

I don't like the supply TVSs being all the way off to the side(s), especially if there's no supply bypass.  That's a good... 100nH maybe?  Don't have a good feel for scale here, guessing that's like a 10cm wide loop?  The left and right legs might be okay but the middle one is maybe at risk here...


I have added in the 2 previous threads to the main post.

Yes its a diode, each block is made of 6 mosfets in parallel plus 1 diode. (3 mosfets on each side)
diode will probably be something like STPS3045DJFY-TR.


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