The underlying problem is that manufacturers of commercial EDA programs have no interest whatsoever in tools that make it easy for their customers to switch to other tools.
oooo I bet that they won't (adopt any other format besides their own)
Regarding GERBERS I think that is probably the UNIQUE common
format among them all..
It would be magic if someone could reverse the GERBER format
into the source ... preferably EDIF (as nobody would like to have
their format excluded)
I bet this will not happen any time soon
Paul
KiCad has the ability to take a set of Gerber files and back-import them into a PCB project.
It is of course not perfect, as there is no concept of "footprints" in gerber files and lots of other info is also missing.
Just for fun I got an old Protel project (with ATmega, Wizznet Ethernet controller and chicken fodder to make it work) and made a full KiCad project out of it.
I had a .pdf of the schematic, so that was mostly completely re-drawing it in KiCad (And redrawing from an example is much quicker then designing a schematic, (for which you have to reference datasheets, decide pin assignments etc).
I converted the set of Gerbers back to a PCB. What you get this way is:
* PCB Outline & mounting hole locations.
* All the tracks in copper.
* Locations of all footprints, which are implicitly encoded in the end points of the tracks.
* Netlist, as KiCad can use DRC to check between differences in the schematic and the actual copper on the PCB.
So after re-entering the schematic, I did the normal footprint assignment and got all new footprints for all components. This was badly needed, because I started with a very old Protel project, and it used a lot of "painting" both for big zones and for pads. Each rectangular rounded pad was made up out of 7 or so line segments, but KiCad has a pretty good PCB editor, so those were relatively simple to delete (I mostly used box select, with dragging from left to right, which only selects items that are completely enclosed in the box)
Moving the new footprints to the locations of the old ones was also pretty simple. You just grab a footprint by a pad, and snap that pad to the end of one of the tracks. All copper tracks that get connected to one of the other pads of that footprint automatically get the name of the netlist, and you can use the Ratsnest function to decide which part you'll do next. This builds the PCB and expands the netlist until everything has it's place.
Near the end I did the normal DRC check, and it got me a bunch of errors. Most were from old garbage (the pad painting) which I had not completely cleaned up. But it also caught a few differences between the schematic and the PCB. It turned out I had made a few errors while re-creating the schematic, and DRC caught that nicely for me.