Strange layout for bypass cap?

[Seán]

Hello,

I have seen a PCB layout where the board has 4 layers where the internal layers are power and ground. In this PCB the person placed a bypass cap (relatively) close to IC power pin (but could be closer), but they don't have it connected directly to the pin itself. Instead they have used vias to connect the cap to the internal power and ground planes.

This seems wrong to me but I am not 100% sure if it is. To my mind, if the cap isn't connected directly to the pin, then it will not be able to supply all the power it can, as some of the power will radiate out into the plane.

As I am, I am not 100% sure, so I am hoping someone can offer some suggestions?

I'm afraid at the minute I can't supply an imagine of the layout, so I hope my description is okay.

Thanks in advance.
Seán

[wraper]

It is right, not wrong. Bypass cap should be between Vcc and GND of the IC, not good if it is near only one of the power pins, and then some loop trace runs to another. And where is the shortest, lowest inductance and lowest resistance path to all of the power pins? Directly through the power planes.
http://learnemc.com/decoupling-for-boards-with-widely-spaced-planes

[Seán]

Fantastic! Thanks for the information!

Seán

[T3sl4co1l]

It makes very little difference where the capacitor is, anywhere on the board.

Indeed, far fewer local-bypass caps are needed, on a 4-layer board, than the number of ICs.

What's always more important is, what is the impedance between IC power and ground pins, and are there any peaks (resonant frequencies) where it's worse?

Putting caps on a parallel plane, or right beside the IC pins, can indeed make things worse instead, by introducing resonances!

It's all a matter of impedance.  Count up the stray inductances, count up the bypass caps, draw the equivalent circuit, and start calculating pairs of Z = sqrt(L/C).  If Z is very different from any nearby ESR (don't forget to put in typical values for capacitor ESR and ESL), it's probably resonating with a large peak at a frequency near F = 1 / (2*pi*sqrt(L*C)).

Common accidents include using too many ceramic capacitors, or aluminum polymer capacitors, both of which have so low ESR that it's almost impossible to avoid resonances -- to put it another way, there's almost no damping in the power supply network (PSN).  It is not only possible, but fairly common, that a PSN has a lower worst-case impedance by adding resistors in series with large ceramic capacitors!

Tantalum capacitors are very popular because they include a modest value ESR, which tends to dampen the network.

There is no point where a large (>1uF) capacitor acts as a "reservoir", not for power quality analysis purposes.  How do I know?  Because the voltage across such a large cap doesn't change one millivolt over the duration of a power line spike!  The wave just bounces off.  Large caps are only relevant for high power circuits, like DC-DC converters and MOSFET gate drivers.

Tim

[PCB.Wiz]

.. In this PCB the person placed a bypass cap (relatively) close to IC power pin (but could be closer), but they don't have it connected directly to the pin itself. Instead they have used vias to connect the cap to the internal power and ground planes.

Missing from this, is how the IC Power pins connect to the Planes ? Did they take a longer path as a result ?
It is ok for the vias to plane to be placed closer to the pins than the CAP, so common is to see Pin-Via-Cap with short traces, and also
Via-Pin-Cap in some cases, where a via can fit within the package area.

Also common, is MicroVia-in-pad designs, where the plane connection becomes harder to see.
This gives highest design density, but tends to be reserved for higher layer counts as it does cost more.

[BMF]

Putting caps on a parallel plane, or right beside the IC pins, can indeed make things worse instead, by introducing resonances!

It's all a matter of impedance.  Count up the stray inductances, count up the bypass caps, draw the equivalent circuit, and start calculating pairs of Z = sqrt(L/C).  If Z is very different from any nearby ESR (don't forget to put in typical values for capacitor ESR and ESL), it's probably resonating with a large peak at a frequency near F = 1 / (2*pi*sqrt(L*C)).
network (PSN). 

Tim

I thought that variations in capacitor values (both by selection and tolerance) along with inductance variation due to trace length had the impact of eliminating high impedances in the spectrum. In that case wouldn't one LC pair dampen another LC pair that is at a different frequency?

[T3sl4co1l]

I thought that variations in capacitor values (both by selection and tolerance) along with inductance variation due to trace length had the impact of eliminating high impedances in the spectrum. In that case wouldn't one LC pair dampen another LC pair that is at a different frequency?

Nope!  You get a delightful valley inbetween, but two peaks aside it, of similar height as before (and spread out slightly from their initially-unjoined frequencies).

Mind that's a very rough average-case assessment.  There are two pairs of possibilities:
C2 >= C1
C2 < C1
L2 >= L1
L2 < L1
Over all combinations of these, you'll see different behaviors, a few of which will happen to reduce max( |Z(f)| ).  But those combinations are most easily predictable by analyzing the network and determining where the losses are (or need to be), and ultimately, it's just harnessing capacitor ESR.  The more general truth is to terminate the network with resistance.

Tim