Author Topic: Paste footprint for this dual MOSFET  (Read 628 times)

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Online HwAoRrDk

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Paste footprint for this dual MOSFET
« on: October 09, 2020, 03:01:10 am »
I am doing a footprint for a dual MOSFET in Vishay's PowerPAK SO-8L package, and I'm pondering what I should do for the solder paste footprint. Pad layout has been done according to the recommended footprint in the datasheet (which is a bit of a WTF, but I digress), but there is no guidance in the datasheet (or any other document from Vishay I can find) for paste footprint. Even with a small-ish SO-8 size chip such as this, I am assuming it would not be a good idea to have the entirety of the large pads filled with solder paste, as there may be too much.

Was thinking of doing something like the attached for paste layer (red areas). Not sure whether I should account for the 'holes' in the top.

Please tell me what you think. Any better suggestions?
 

Online HwAoRrDk

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Re: Paste footprint for this dual MOSFET
« Reply #1 on: October 10, 2020, 02:28:28 am »
Upon further thought, perhaps something like this instead.
 

Offline dunkemhigh

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Re: Paste footprint for this dual MOSFET
« Reply #2 on: October 10, 2020, 03:24:36 pm »
Why is that better?

(Just curious!)
 

Online T3sl4co1l

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Re: Paste footprint for this dual MOSFET
« Reply #3 on: October 10, 2020, 07:46:57 pm »
I wouldn't worry about it either way, just use a reduced size blob.  Solder flows fine.

Spreading things out a bit may still be worthwhile with lead-free, YMMV.

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Online wraper

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Re: Paste footprint for this dual MOSFET
« Reply #4 on: October 10, 2020, 07:53:50 pm »
Upon further thought, perhaps something like this instead.
It's not better. if anything, it will only help to entrap escaping gasses during reflow. Which in turn will increase solder voiding or even lift the chip from it's place during reflow.

« Last Edit: October 10, 2020, 08:02:20 pm by wraper »
 
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Online HwAoRrDk

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Re: Paste footprint for this dual MOSFET
« Reply #5 on: October 12, 2020, 09:01:31 am »
Why is that better?

I dunno. :) I just thought it might be better to ensure that the 'legs' that connect to the external flange were fully soldered.

I wouldn't worry about it either way, just use a reduced size blob.  Solder flows fine.

It's not better. if anything, it will only help to entrap escaping gasses during reflow. Which in turn will increase solder voiding or even lift the chip from it's place during reflow.

Okay, thanks. I guess a single smaller rectangle is just fine, then. Definitely don't want any voids, as the copper on the PCB is supposed to be providing the heat sinking, and I want maximum heat transfer. This is my first time having to do my own solder stencil pattern for a non-trivial footprint, so I really have no experience to go on apart from knowing that for large pads you don't fill the whole area with solder.

Will probably still have a separate rectangle of solder for the external flange, just to ensure that gets soldered properly.
 

Offline Pseudobyte

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Re: Paste footprint for this dual MOSFET
« Reply #6 on: October 12, 2020, 12:56:15 pm »
I guess there are two schools of thought for paste.

Completely control your apertures using a 4 mil stencil as the thickness of the paste. Which means you need to window your large pads.

or

Leave your paste mask 100% of the pad then find yourself a good CM, who to ensure IPC soldering requirements will correct the apertures.
We mess with customer paste files all the time. As a CM we know what works and what produces defects.
We will reverse-homeplate discretes and also properly segement large apertures for venting and paste reduction. We also correct paste size on BGA's and LGA's
“They Don’t Think It Be Like It Is, But It Do”
 

Online wraper

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Re: Paste footprint for this dual MOSFET
« Reply #7 on: October 12, 2020, 01:11:38 pm »
as the copper on the PCB is supposed to be providing the heat sinking, and I want maximum heat transfer.
Solder paste pattern will not make any difference for that unless you get some very extreme voiding. Just use what manufacturer suggested and you'll be fine. You should consider that PCB cannot transfer too much heat away to begin with. So thermal interface between part and PCB can make only a miniscule difference in the grand scheme of things.
 

Offline voltsandjolts

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Re: Paste footprint for this dual MOSFET
« Reply #8 on: October 12, 2020, 01:15:26 pm »
You should consider that PCB cannot transfer too much heat away to begin with.

I would disagree with that assertion. For pulse applications, PCB copper can save the day.
 

Online wraper

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Re: Paste footprint for this dual MOSFET
« Reply #9 on: October 12, 2020, 01:17:36 pm »
Leave your paste mask 100% of the pad then find yourself a good CM, who to ensure IPC soldering requirements will correct the apertures.
We mess with customer paste files all the time. As a CM we know what works and what produces defects.
And I want to kill stencil producer every time they mess with center pads on my stencils containing QFN with LGA style pads on it's corners. Thanks for solder squeezing out from the corners  :palm:.

 

Offline voltsandjolts

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Re: Paste footprint for this dual MOSFET
« Reply #10 on: October 12, 2020, 04:01:11 pm »
Library Expert Pro does this for DPAK footprints.
Free version doesn't have PowerPAK SO8 but it would likely be similar.
 

Offline Pseudobyte

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Re: Paste footprint for this dual MOSFET
« Reply #11 on: October 13, 2020, 01:02:17 pm »
And I want to kill stencil producer every time they mess with center pads on my stencils containing QFN with LGA style pads on it's corners. Thanks for solder squeezing out from the corners  :palm:.

Since we operate turn-key our customers never see the stencil. Plenty of newer production lines also have paste jetting capability and make these modifications on the fly.
If you want to see a serious bit of electronics assembly kit, check out mycronic's MY700.

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Offline Kasper

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Re: Paste footprint for this dual MOSFET
« Reply #12 on: October 15, 2020, 05:50:57 am »
For the 2nd option that op shared, would you worry about flaps in the stencil? 

Just south of the upside down U's near the north edge.
 

Online HwAoRrDk

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Re: Paste footprint for this dual MOSFET
« Reply #13 on: October 15, 2020, 11:17:50 am »
True, I hadn't noticed that one would form unsupported flaps. I guess it's probably unwise to ever have any stencil aperture that is a concave polygon, so I shall have to remember that.

Not going to use that option anyway, so a bit of a moot point.
 

Offline Kasper

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Re: Paste footprint for this dual MOSFET
« Reply #14 on: October 15, 2020, 02:45:59 pm »
I'm not sure if that would be a problem.  Can't recall ever seeing one like that.  I could imagine bending the flap while cleaning the stencil but I'm not sure how the pros clean them so it might be fine.
 

Offline exmadscientist

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Re: Paste footprint for this dual MOSFET
« Reply #15 on: October 17, 2020, 10:56:46 pm »
Nexperia's SOT1205/LFPAK56D package is nearly identical to the Vishay PowerPAK SO-8 Dual but includes a suggested paste layer.

I forget if NXP/Nexperia did compatibility tests on the dual version of this package, but I know their footprint for 5x6 singles is suitable for soldering multiple manufacturers' parts to with excellent yield. See also ONSemi's AN9137/D, which describes a slight tweak to the NXP footprint to produce the most universal version of it that I know of.
 

Online HwAoRrDk

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Re: Paste footprint for this dual MOSFET
« Reply #16 on: October 18, 2020, 12:34:45 pm »
Interesting app note, thanks.
 


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