Weird.
OK, The PDIe Add in connector has power, JTAG, I2C and PRESENT#1 to the left of the keyway.
To the right of the keyway, there are lanes 0-3 then the PRESENT #2 signal. Then lanes 4-7 with another PRESENT#2.
Finally for the *16 connector, we have lanes 8 to 15 and after them PRESENT#2 again.
The idea is that you short PRESENT#1 to PRESENT#2 on your add in card and the host uses this to determine the size of the card in the slot.
The other thing you need to know is that (Optionally IIRC) PCIe buses are reversible. If lane 0 doesn't come up then the root complex may use lane 15 as lane 0, lane 14 as lane 1 etc.
Looking at that card, this is exactly what Lenovo have done. You can see the diff pairs going between the chip and lanes 15 to 12 on the edge connector.
They've gold fingers where they need them to short out all the PRES#2 signals.
Where there is no signal running across the connector, they have completely removed the edge conn.
Your guess as to why they did that is as good as mine. Save on gold / reduce insertion force / remove capacitive stub from unused high speed lines. 'Tis very odd.
There is nothing strange about those capacitors.
They are spaced deliberately above the PCB.
Electrolytic capacitors do not like heat, and soldering is pretty hot.
By making the leads a bit longer and spacing the capacitors they receive significantly less heat during soldering, and this improves long term reliability.
The fact that they use through hole capacitors which are harder to place than SMD (Drilling all those holes in the PCB, possibly bent legs during insertion, wave soldering instead of reflow) could already be an indication that lenovo wants to design a reliable product here. THT elco's are generally of higher quality than SMD ones, but a good SMD cap is of couse still a lot better than a bad THT cap.
Electrolytic capacitors are also the most unreliable electronic components, except maybe for connectors which face the harsh outside world and mechanical stress from insertions.
