Author Topic: PCB layout and stackup for space application  (Read 945 times)

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Offline Luca_Daidone

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PCB layout and stackup for space application
« on: January 24, 2022, 11:31:04 pm »
I've been tasked with the design of a PCB for a CubeSat project in my university and I'm trying to figure out exactly how the layout and stackup of my board should be done.

The board I have to design is for power distribution, this means that on the board there will be mainly DC DC converters and an IC for battery management. I forsee that 4 layers will be needed.

For the design I must take into account the ECSS guidelines (European Cooperation for Space Standardization) and I've been studying the relevant standard (https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwimyPfI88r1AhXRR_EDHbduCWcQFnoECAYQAQ&url=https%3A%2F%2Fescies.org%2Fdownload%2FwebDocumentFile%3Fid%3D62466&usg=AOvVaw3rpnrTAX8y84w2E_JSMVfm&cshid=1643045117480261). I'm extremely confused by few of the rules listed on the document, for example:

7.4.3 point e) Tracks should not be routed on external layers.
13.9.3.3 point b) In case critical tracks are routed on external layers, they shall not be routed under components.
I guess this is to improve EMI and radiations immunity but it means that the stackup of the board can't be like the "standard" stackup (signals on external layers and internal GND/power planes) but must be something like GND on top and bottom layers and signals&power in the inner layers.

I understand the upsides of this stackup (two ground planes can be stitched together around the periphery of the board to enclose all the signal traces in a faraday cage, signals and reference plane very close to each other etc.) however I can't really imagine to place a via for each signal coming from every smd pad: it looks like a routing and signal integrity nightmare to me.

For example the feedback loop of a DC/DC converter must be routed as short as possible and going from the top layer to the middle one and coming back to the top layer doesn't sound very wise to me.

Also so many vias means many via stubs acting like antennas. Probably an hybrid stackup would be better (signals and ground on top layer) but then why not going with the "classic" stackup.

7.8.2.2 point a)Solder mask shall not be used.
7.6 point a)Copper planes should have additional openings in a grid format.

Since outgassing it's a big issue in space applications, they forbid the use of soldermask and suggest to apply a layer of conformal coating after the assembly. Also they suggest hatched polygons in order to allow humidity to get out of the board easily.

These points puzzle me a lot since all the boards we're buying from the industries, rated for space, come with solder mask, no conformal coating and full polygons. Also I'll be probably soldering the firs prototype and I'm afraid that by having no solder mask the tin will flow away from the smd pads.

Do you think that a stack up with signals only on internal layer is feasible? Are via stubs and feedback loop length a reasonable concern at the frequencies at which the DC/DCs are working? Do you have experience with such design? Should I remove the solder mask completely or maybe only on few spots?

These guidelines don't really make sense to me but I can't play by my own rules without justifying them first to the team.
« Last Edit: January 25, 2022, 11:34:10 am by Luca_Daidone »
 


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