PCB prototype with small 0.35mm pitch BGA chip

[andan42]

I'm sorry if I asked this question in the wrong place, this is my first question here and I'm not sure where to go.
My prototype requires a tiny BGA chip with 4x7 balls, with 0.35mm pitch (max86171) for which I couldn't find any alternative. The datasheet mentions a 0.2mm pad with 0.15mm between pads.
I've contacted JLCPCB support and they said 0.35mm pitch BGA is possible, and suggested I could use in pad vias (which they can do), but given the minimum via drill and annular ring (0.2, 0.35) that seems impossible (pad INT2 in the screenshot).
Routing on the top layer only seems impossible if I use the 0.2mm pad size as given in the datasheet (given 3mil/3mil trace width and spacing, see screenshot).
Is it a decent idea to reduce the copper pad to 3mil (0.077mm), with a 0.2mm solder mask opening? That seems to allow all the traces to go on the top layer, since the ball grid isn't deep at all.
Do you have any ideas of a quick and dirty way to get a prototype with such a chip working within a reasonable budget (ideally $50 - $100) or did anyone try something similar in the past?
Thank you for reading and I'm looking forward to hearing your thoughts on this!

[wraper]

First of all this does not work according to their BGA capabilities, not even minimum trace width and spacing (0.09mm). However they offer free via in pad for 6-20 layer PCB. You should ask them if they can do via in pad of such size and what is actual minimum hole/annular ring size.

[andan42]

Thank you for the reply! Yes, the BGA listed in capabilities is a bit larger than this but JLCPCB support said it was possible (not sure how).
I should've clarified, the attempt at making it work with just 0.77mm (3 mil) traces and no vias was hoping I could find a manufacturer (other than JLCPCB) that does 3/3 traces and spacing, and maybe avoid the cost of vias in pads. Not sure if that was a good idea, I'm just trying to consider both via in pad and routing on top layer to see which would be easier to get done.

[wraper]

I don't think there will be any cheap way other than done by JLCPCB. Since you got a suggestion from them to use via in pad, ask them if they can actually do it for footprint of this size.

[andan42]

Asked details from JLCPCB, if they tell me their recommended way to do it I will go with that. NextPCB lists 3/3 mil trace (rounded to 0.8mm) though. Is the hacky idea of using smaller pads than the datasheet with normal sized solder mask openings a decent alternative if nothing else works?

[wraper]

NextPCB certainly can produce it in proper way, however most likely it will include a lot of extra cost.

[andan42]

Thank you very much for the insight. I'm relatively new to PCB design and this kind of information is hard to process, even when looking at capabilities pages.
For manufacturing with NextPCB, would you recommend using top layer traces, in pad vias or tented vias near the pads? Or something else? Sorry if I'm asking silly questions, but I'm having a hard time understanding which approach is more realistic. Basically I'm not sure if smaller traces are roughly the more accessible capability or smaller vias are the more accessible capability.

[wraper]

NextPCB claims to do laser blind vias.

[Kasper]

Just discussed 0.4mm bga from jlc here:

https://www.eevblog.com/forum/eda/is-a-6-layer-board-with-cabga381-chip-diy-able/

[andan42]

I checked the post, but my issue with the 28 pin 0.35mm pitch is also that I can't (don't know how to*) really route the middle pins to the outside. Basically trace spacing and sizes don't allow it while Vias (even In Pad) would seemingly be at lest 0.35mm, which is already huge if you look at the pitch. As far as I've seen in your post you dealt with 4 pin small pitch chip as well as bigger pitch BGAS, no?

[Kasper]

Yes, mine was just 4 pin so routing was easy. 

Sounds like jlc has vippo (via in pad plated over).  That should get you to inner layers for fan out.

Try smd (solder mask defined) pads to get closer to their capabilities.

Break some rules if you have to and hope they'll tell you and suggest improvements if it's really a problem.

[andan42]

Yea I just asked their support and they told me the minimum via (2.5mm) which is smaller than what I found on the capabilities page. I think that might be enough to get this to work with minimum rule breaking? Still not sure if I have the right approach.

[Kasper]

Have a thurough look at their capabilities page.  If you want more details, Tempo automation has a well detailed capabilities page that I found helpful.  They of course have different capabilities but it describes them well.

[Kasper]

Since they told you their min, use that and give less priority to the other rules.

[Sagar]

In past i have tested the JLCPCB capabilites, the listed capabilities on the website are not bare minimum. We can push the limits to some extent, as I have done with my designed cut-out board. If you are finding the lowest priced one JLC is the solution but you have to atleast order once to test them out at your own risk if you are planning for bulk.

[Doctorandus_P]

IMHO the best response is to first go curse at IC manufacturers for a while for designing packages like this, and then buy some other part.

[free_electron]

IMHO the best response is to first go curse at IC manufacturers for a while for designing packages like this, and then buy some other part.

nope. this is a flip chip for cell phone and tablets apps. VIPPO and ELIC process. Laserdrilled and 1/4oz copper on glass-free substrates. Apple / Samsung do this all the time. Mass production technology.

[Doctorandus_P]

I heard of VIPPO (Via in Pad Plated Over) but ELIC (Every Layer Inter Connect) was new to me. After some more reading it looks like it is a lot like LTCC (Low Temperature Co-fired Ceramic) but without the ceramic. 

It does make more sense once you start realizing packages like these are not intended to be used on regular FR4 (and common resolutions used for FR4).

[free_electron]

I heard of VIPPO (Via in Pad Plated Over) but ELIC (Every Layer Inter Connect) was new to me. After some more reading it looks like it is a lot like LTCC (Low Temperature Co-fired Ceramic) but without the ceramic. 

It does make more sense once you start realizing packages like these are not intended to be used on regular FR4 (and common resolutions used for FR4).

You can do ELIC with regular pcb material too. I made a tiny 6 layer board that held a flip-chip BLE-psoc, spi flash and a number of sensors including accelerometers and gyro.

The whole asembly, including supercap for power was the size of a stimorol chewing gum pellet. The idea was to stick it behind the ear of football player (american hand-egg version) and measure the shocks they were subjected to. It recorded the energy vector (magnitude and 3d vector of impact) for later analysis. wireless charging using board-embedded coil. (wasn't very efficient but didn't matter)

It would only "talk" over BLE when in its charging case. Removing it from the charger shut down the ble and it went into recording/ ultralow power mode. Silicon was flip-chip. They programmed players id into the device. post-game the units were "sealed" (further recording blocked) and then the data could be dumped. Used as evidence. The charging case held all units for the entire team and had it's own battery pack so it was not main power dependent.

Was kinda cool to do a board where you could really go vertically anywhere you wanted. No vertical restrictions and no pesky vias eating space anywhere.

[hghadia]

Looking at the layout, it seems tight but doable.

Copper Pad Size: Reducing the pad to 0.1mm might work, but it risks poor solder joints. Keep it as a last resort.

In-Pad Vias: They might be challenging with your current setup due to drill size. If possible, use filled vias to prevent solder wicking.

Routing: Try using a thinner trace width (2mil/2mil if your manufacturer can handle it) to route more signals on the top layer without reducing pad size.

This layout is close to the limits, so prototype carefully to validate it. I suggest discussing this with Aaloktronix as well.

[Psi]

Can you design your prototype to accept a small dev/eval board that already exists on the market for that chip? Attach it with headers or something.

I've seen people do that to avoid getting into the HDI pcb territory for a prototype.


Could even dead bug it under a microscope with tiny wires then cover in epoxy for a prototype.
That would require some skill, but it's definitely possible.


The last time I had to do a HDI pcb for work that had buried/blind via's and via-in-pad we got 10 prototype boards and it cost ~$1000.  Was for the STLED524  LED matrix driver IC.  CSP 56 bumps 0.4 mm pitch 3.4x3.0 mm.   That was like 8 years ago. So probably cheaper now.  I think it was from PCBway