PCB Stackup Planning and Materials Selection Tools

[Damperhead]

I'm interested in how much Forum readers use the PCB Stackup Planning and Materials Selection tools. I think they are a great help in circuit board design and especially in specification.

I have experience with iCD Stackup Planner and Z-planner and I find them very useful tools in PCB material planning. Polar also has its own software for defining PCB stackup called Polar Speedstack.

• iCD Stackup Planner: https://www.icd.com.au/SP.html
• Z-planner Designer:  https://www.z-zero.com/z-planner-designer/
• Polar Speedstack: https://www.polarinstruments.com/products/stackup/Speedstack.html

[PlainName]

I notice that none of those display even ballpark pricing. Typically, if you have to ask then they expect you to have a personal money tree.

[Damperhead]

Here are my rough estimates of the prices:

iCD Stackup Planner: ~5k€ + options
Z-planner Designer: ~10k€
Polar Speedstack:  ~10k€ or even more

However, these are professional software intended for businesses, so the prices are not exactly at the cheapest end.

[PlainName]

Thanks. I realise they're not meant for someone etching in the garage

[tszaboo]

Here are my rough estimates of the prices:

iCD Stackup Planner: ~5k€ + options
Z-planner Designer: ~10k€
Polar Speedstack:  ~10k€ or even more

However, these are professional software intended for businesses, so the prices are not exactly at the cheapest end.

I myself am not working with that complicated stackups, for a tool like this to be worthwhile.
Altium has something with basic functionality, that's enough for 100% of my needs.

[nctnico]

Here are my rough estimates of the prices:

iCD Stackup Planner: ~5k€ + options
Z-planner Designer: ~10k€
Polar Speedstack:  ~10k€ or even more

However, these are professional software intended for businesses, so the prices are not exactly at the cheapest end.

An Orcad PCB designer license, which has such a tool included in the cross section editor costs less than those software packages.

[asmi]

Here are my rough estimates of the prices:

iCD Stackup Planner: ~5k€ + options
Z-planner Designer: ~10k€
Polar Speedstack:  ~10k€ or even more

However, these are professional software intended for businesses, so the prices are not exactly at the cheapest end.

Wow, I wonder what kind of business can justify such insane prices, especially since companies tend to standardize these kinds of things, and in any case they always have an option to request that information from PCB fab they work with for free if they require something out of ordinary, as nowadays most PCB fabs' standard stackups are fairly good for most designs. I personally can't think of a business which would justifiably need this, except for PCB fabs.

[asmi]

An Orcad PCB designer license, which has such a tool included in the cross section editor costs less than those software packages.

So does Altium Designer - they licensed a 3D field solver from Simberian and integrated it into their Layer Stack Manager.

[Uky]

There is a difference between layer managers where trace impedances, board thicknesses, etc. can be calculated
and "real" planners that take possible via spans over several layers, blind and buried as well as maintain tables for dielectric
thicknesses and baking combinations into account. The best thing to do after realizing that a complex multi-layer board is needed
is to contact the board manufacturing factory and ask "What are your most popular build-ups" in terms of dielectric and prepreg
availaibility, plating procedures and the combination of baking in several steps (intenal layer via spans). When I deal with
10 or more layers, it is a must. I also get recommendations regarding the materials and the qualities that moves more often.
This can be important, since prepregs stiffens as they age which affects trace impedances if inner traces are routed with a prepreg as
one of the dielectric layers.

 

[nctnico]

That only works if you know the board manufacturer in advance. I'm always confronted with whatever an assembler manages to find. I just check whether the board can be produced within the specs based on the (slightly) different stackup the board manufacturer offers. Typically I go from a standard buildup from a big manufacturer assuming that such a buildup is commonly used. Which has been the case so far with only minor differences (slightly different materials and core / prepeg thicknesses that vary 0.02mm or so).

[Uky]

That is indeed true. In most cases, the customers I work for has a long term relationship with "their" board manufacturer
which saves me the hassle from searching for stackups myself. When the assignment is about to start; i approach the
manufacturer and we establish a dialog which saves me and the board manufacturer from unneccessary extra work.

 

[nctnico]

That would be so nice... Some of my designs have been produced by at least half a dozen different manufacturers and at one point a PCB manufacturer did manage to mess up the production of a board for a rather large production run. No happy faces and lots of finger pointing. BTW, it is interesting to see how much variation there is in trace widths between various PCB manufacturers based on the exact same layout. So even with a well defined stackup, etc there will be a large tolerance in the actual impedance of the traces.

[Damperhead]

This eBook can increase your knowledge of stack-up design. The information is relevant especially if you are dealing with hi-speed links like high-speed Ethernet PAM4 protocols, including 25GE, 50GE, 100GE for example.

http://i-007ebooks.com/my-i-connect007/books/printed-circuit-designers-guide-stackups-design-within-design/

[asmi]

That would be so nice... Some of my designs have been produced by at least half a dozen different manufacturers and at one point a PCB manufacturer did manage to mess up the production of a board for a rather large production run. No happy faces and lots of finger pointing. BTW, it is interesting to see how much variation there is in trace widths between various PCB manufacturers based on the exact same layout. So even with a well defined stackup, etc there will be a large tolerance in the actual impedance of the traces.

To help with that, if I know that the PCB might end up being manufactured all over the place, I target an impedance value closer to a lower bound of impedance tolerance window in my eCAD, this creates traces which are a bit wider than ideal, and so manufacturer can make them narrower if required for his process/stackup. This is OK because you can always make traces narrower, but often you can't make them wider without violating spacing and/or increasing risk of problems related to crosstalk.

[electronx]

I have been suffering from this issue lately
I have worked with different manufacturers, some say that production is possible, some say that it cannot be produced, some say that they have the relevant prepreg, some say that they do not

Another problem is that it is very difficult to access the datasheets of prepreg or core materials
At least the thickness information and min information after lamination is required
I have to beg from the manufacturers one by one

Actually it should not be this difficult
Other issues are that they cannot go down to 0.06 mm trace thickness in 1 oz copper, they want 0.5 oz due to etching

It would be nice if at least one tool could provide all the thicknesses after lamination

and create a stackup that can be produced from the existing materials when the relevant impedance requirements are entered

[Damperhead]

Yes, many PCB material manufacturers do not necessarily openly share their line up of core and prepreg materials and what kind of copper thicknesses and roughnesses are available for them.

Isola shares line up information on their website for the most common materials (370HR is a good starting point.) Many eastern manufacturers such as Shengyi, EMC and ITEQ follow them and corresponding materials can be found.

A good starting point is to ask for a quote or something like that on Isola's stack up but they can change material suppliers but keep the layer thicknesses the same.

The final pressed thickness is affected by the resin content and the copper etching rate. Mainly the etching rate. An easy rule for this is to subtract -4µm - 6µm from the pre-preg thickness if the copper filling rate is 90% -100% if the copper filling rate % is less then the number is usually bigger 5µm - 10µm or even more. (Rule of thumb)

Trace width usually depends on the components used. Larger >0.8mm pitch BGA components can be routed using a 100µm trace width. Smaller BGA packages 0.5mm  or 0.4mm pitch with a large number of balls may require laser drilling and thinner trace widths.

100 µm trace width and 150µm trace isolation (gap) is a fairly safe starting point for 1oz inner layers. Under BGA areas you may have to compromise a little on the gap, such as 100µm.

My own view is that in a properly designed PCB that contains normal, carefully selected components, there is no need to make any compromises with productivity. Miniature electronics is then its own art form, Mobile phones, tablets etc.