Author Topic: PCB track layout - is a 3.3 Mhz voltage boosting capacitor hazardous to signals?  (Read 1061 times)

0 Members and 1 Guest are viewing this topic.

Offline badrequest400

  • Newbie
  • Posts: 3
  • Country: gb
I'm a hobbyist designing my first PCB (two layer) and I'm wondering about interference between currents in tracks that I've placed somewhat haphazardly.

In the attached image, C5 and C6 are used by a chip called SSD1306 to boost a 3.3 V supply into 7 V for an OLED. It occured to me that maybe the pulses of current might cause interference in the clock signal coming from the microcontroller since the tracks for chip select and the SPI clock are running underneath the capacitors. It looks easy enough to move them a little away from those capacitors but if that's needed, how far do they need to be? Am I worried about nothing?

Page 8 of this datasheet seems to suggest the capacitors will have oscillations at 3.3 MHz

The SPI clockspeed would normally be 4 MHz but I'm hoping to reduce the MCU clockspeed to save power which will also reduce SPI clockspeed. I'm not yet sure how much I can reduce it without adversely affecting something but I don't know whether it's relevant to inteference. Thanks for your attention.

Online T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 19295
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
No, those won't be logic output pins nor will they be running at 3.3MHz.  That figure is for the logic (SPI bus) pins when toggling at that rate.

There's nothing you can do about the coupled length in the flex cable itself, anyway.  No need to be any fancier on the PCB.

The best thing you can do is provide isolation between signals, by pouring ground around/under them.  Hair-thin ground traces are a far bigger curse than where the charge pump traces are routed!

Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!

Offline badrequest400

  • Newbie
  • Posts: 3
  • Country: gb
Okay, thanks, Tim. I've increased the thickness of the power/ground traces. I also moves the traces for the two capacitors closer together to get their emissions to cancel each other a bit.

Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo