EDA > General PCB/EDA/CAD Discussions

PCB with Virtex 5 FPGA's

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diracshore:
Ok, couple of things to address.

First yes I found some of tinheads comments abrasive. But I have learned to filter this type of thing when gleaning information from forums. I have to consider attitude irrelevant mainly because those people in possession of the most pertinent knowledge typically have character flaws, case in point. tinhead actually provided me a great deal of relevant info and for that I am grateful. But I hear what you are saying David.

The board I aquired for $100. Also note they are ES / early silicon / engineering sample chips. And where $15k might be the going rate for the commercial version, from a US vendor say Avnet, the truth is those people who need ES parts can get the LX330 from the black market in Taiwan at about $300 a pop sans PCB, and the commercial version can be had from legitimate sources for about US$5k. Not that there would be much point in using virtex 5 vs virtex 7 in a new design.

Now I don't know if these chips even work. So powering the board and connecting the JTAG is the path of least investment to verify that. I doubt that just hooking up a JTAG would kill the FPGAs and I know this type of hack has been done before. See here.

http://nsa.unaligned.org/hw.php

I plan to try to use some of his techniques to commandeer the virtex FPGA's with just a few IOs. While I am not interested in hash cracking, the application I would use for these chips, assuming I get them running, would be risky in itself to the FPGA. Evolutionary hardware (my interest) requires a large fabric and it has to be expendable.

I'm not a hardware guy and I need help with this stuff. I have a multimeter, a open source logic analyzer, and a small budget.

The logic analyzer I plan to use you can see here,

http://www.seeedstudio.com/depot/preorder-open-workbench-logic-sniffer-p-612.html?cPath=75

Anyway Thanks to everyone for their time.
Thom

tinhead:

--- Quote from: diracshore on August 09, 2011, 12:02:20 pm ---tinheads comments abrasive.

--- End quote ---
^^ Thom, you welcome.


--- Quote from: diracshore on August 09, 2011, 12:02:20 pm ---But I have learned to filter this type of thing when gleaning information from forums.

--- End quote ---

no, that's the wrong way, just listen careful what ppl trying to tell you, forget any kind of emotions
and don't take personal any kind of comments.

You can see this in a different way - ppl with more knowledge are probably older than
you - so they will die first :)


--- Quote from: diracshore on August 09, 2011, 12:02:20 pm ---The board I aquired for $100. Also note they are ES / early silicon / engineering sample chips.

--- End quote ---

oki, then forgot my ebay proposal as you bought for reason.


--- Quote from: diracshore on August 09, 2011, 12:02:20 pm ---Now I don't know if these chips even work. So powering the board and connecting the JTAG is the path of least investment
to verify that.

--- End quote ---

as i said above, you will find in Virtex datasheet possible core and i/o voltages, additionally all these DC converters
are good known so not a big deal to find out which DC is for what voltage and how connected (FPGA or other things).
You should as first step cleanup the board, there are some shrots, broken PCB, broken parts. I would also
remove both Broadcom chip, the Netlogic chip, the PPC chip, the Vitesse chip,
the Actel Fusion chip (you can reuse this baby, that's mixed signal FPGA (probably - i don't see exact) with ARM core)
and eventually the small board with PIC controller - this is, let me gues, power contolling unit.
You have multimeter, so you can check if Dc converters power good/enable pins are routed to that small board.

Then take a closer look on the small chips, look for configuration devices - when non there then the firmware
is uploaded by ┬ÁC/CPU or Actel Fusion (however it will be somewhere stored).
In any case you have then to find the JTAG plug/pins/signals - with some luck easy job.

Having cleaned-up board you can then play with powering up. My proposal does not have anythign to do with pure power
consumption, the last thing you need is a FPGA with loaded firmware or chips locking pins .. why see below.


--- Quote from: diracshore on August 09, 2011, 12:02:20 pm ---I doubt that just hooking up a JTAG would kill the FPGAs

--- End quote ---

to scan the chain over JTAG will not destory anything ... but (see below) ...


--- Quote from: diracshore on August 09, 2011, 12:02:20 pm ---and I know this type of hack has been done before. See here.
http://nsa.unaligned.org/hw.php

--- End quote ---

... something like boundary scan can definitely shot some pins.
During boundary scan you can check the register to see their status, but you can also change
the i/o cell (actually pin) status. So when two chips are driving as output the same wire between them you
can easily burn both.

My proposal, there are profesional tools like Universal Scan from Ricreations - use such tool.
The 30days version is good enough ... when you need more use google.
In this tool you can easily play safe with boundary scan, monitor pin status and apply (in extest mode) some
values to pins to check interconnectivity between FPGAs and other chip (or the pads where these chip was soldered).


--- Quote from: diracshore on August 09, 2011, 12:02:20 pm ---and I know this type of hack has been done before. See here.
http://nsa.unaligned.org/hw.php

--- End quote ---

this tool was designed to make boundary scan easier on a bord with MULTIPLE FPGAs or Boundary Scan capable chips,
believe me it is a hell of work when you have more than one chip to reverse.

On your board there are 3 FPGAs, but probably not even connected together - additionaly bunch of chips without JTAG.
So forget that tool, unsolder these few parts (or maybe even more - however i can't see all
of them detailed to tell you what can/can't be removed) and use Universal Scan to test
the "free" i/o pins. When you have some chips removed you can then see in universalscan
what is the status of input cell - based on that (when they not changing after power up - that's why you should
find the way how the FPGA design will be uploaded, to interrupt it) you can create a map of free i/o pins,
then set them to Z and measure the free pad voltage . if something connected the voltage will be different as when nothing connected ... there are many tricks you can use,a nyway, let's start first with power supply.


--- Quote from: diracshore on August 09, 2011, 12:02:20 pm ---I plan to try to use some of his techniques to commandeer the virtex FPGA's with just a few IOs.

--- End quote ---

so then it make sense to remove all unnecassary chips, as i said above.
Btw, you can leave these GSI memory chips soldered - you might have a use for them, fast memory (even if these FPGAs are huge)
is always good thing.


--- Quote from: diracshore on August 09, 2011, 12:02:20 pm ---I'm not a hardware guy and I need help with this stuff. I have a multimeter, a open source logic analyzer, and a small budget.

--- End quote ---

small budget = hmm, with some luck you will need only one input voltage for all DC converters.

multimeter = be careful, some multimeters have much too high voltage while in continuity test mode.
To high voltage will shot i/o pins, check first the manual or measure (when you can) the voltage.

I'm using continuity tester with 0.3V, so even with wrong polarity nothing can be damaged.
When i look on my multimeters, some have 10V while within continuity  test .. this is of course overkill.
The best would be below 0.7V


--- Quote from: diracshore on August 09, 2011, 12:02:20 pm ---The logic analyzer I plan to use you can see here,

http://www.seeedstudio.com/depot/preorder-open-workbench-logic-sniffer-p-612.html?cPath=75

--- End quote ---

oh yeah, that's the Sump modified design. Actually you could use the small Virtex to buld a kick-ass Logic Analyzer
based on that Sump design but you will need ISE license, the web edition will not work .. ups, you need it anyway.

diracshore:
That is incredibly helpful. I have a very clear idea of a plan now.

Thank You 1000 times tinhead !

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