PCBWay issue with QFN solder bridge, what to do?

[VEGETA]

Hello,

I have TPS54394 IC with the QFN 16-pin package. PCBWay gave me this email:

Thank you for your order xxxx to PCBWAY. This is yyyy, your service representative.


After checking your file, we found that IC distance did not reach to 0.22mm, we can not  do the soldermask

bridge, Here are some solutions
1. Change IC distance to 0.22mm
2. With IC distance less than 0.22mm, we do not do soldermask bridge, but it will be easy short for assembly

and with a picture attached here.

What I understood is that they offer solder mask between pads up to just 0.2mm or 0.22mm but not less... my design IC have less (about 0.15mm) and they suggest that I either change the pad size or just remove solder mask between these sections.

I read that removing solder mask of tiny components is an ok behavior but wanted to verify.

this product will be manufactured to be soled later on, this time just a test board.

Note: my pads are the accurate size, solder mask on each pad is the same size as the pad. I have no problem with removing the solder mask bridge of that area if it helps.. and this product will never be manually soldered or assembled, all by fab house and assembler service.

best regards,

[ataradov]

It is fine, you can just tell them to proceed with manufacturing. They can't make reliable solder mask bridges, but in many cases they would be made. Some of them would likely break, some will stick.

I always keep those bridges in my gerbers. May be one out of 10 ties they would complain, other time they just make the board without asking.

For prototypes it does not matter, for mass production - you need to figure this out with your PCBA house.

[Feynman]

Are you sure your footprint is correct? In the picture it appears that the pads in x-direction have more distance to each other than the pads in y-direction.

[wraper]

There is something wrong with your footprint if you need 0.15 mm solder resist bridges for footprint with 0.65mm pin pitch. Even JLCPCB makes solder resist bridges for 0.5mm pitch QFN. I personally usually supply gerber files with 1th solder mask clearance and let the fab do their best by adjusting according to their process, instead of making larger on my side. Never received a complain that gap is below minimum allowed. Surprisingly usually they do much tighter gap than their websites claim. Also note that if pads are wider than they need to be, likely you will have solder bridging problems.

[ataradov]

On a second look, yes, the footprint looks busted.

TI site just made me hold a button for 10 second to prove that I'm not a bot. What a joke.

[wraper]

TI site just made me hold a button for 10 second to prove that I'm not a bot. What a joke.

Did not ask me anything but let me wait a whole minute while it checks I'm not a robot.

[wraper]

On a second look, yes, the footprint looks busted.

Looked on it again with more attention, horizontal and vertical pin pitch are different  .

[VEGETA]

Are you sure your footprint is correct? In the picture it appears that the pads in x-direction have more distance to each other than the pads in y-direction.

I downloaded it directly from TI, the link is via Ultralibrarian. Downloaded it again now to verify and it was the same one as I used.

However, I saw that in datasheet they are the same. 0.65mm between them, but the ones in other direction in the footprint I downloaded are 0.5mm.

[ataradov]

The footprint is wrong. This happens all the time with those library things.

[VEGETA]

The footprint is wrong. This happens all the time with those library things.

you are correct! footprint is wrong and I fixed it now by using

Package_DFN_QFN:QFN-16-1EP_4x4mm_P0.65mm_EP2.7x2.7mm_ThermalVias

from kicad official library.

guys please check this one and give me feedback if it fits nicely, more eyes are better. I attached the snapshot.

[ataradov]

It looks fine. And given that PCBWay did not complain about other dimensions, you are likely to be fine with solder mask bridges.

[SiliconWizard]

Are you sure your footprint is correct? In the picture it appears that the pads in x-direction have more distance to each other than the pads in y-direction.

I downloaded it directly from TI, the link is via Ultralibrarian. Downloaded it again now to verify and it was the same one as I used.

I personally do not trust stuff from Ultralibrarian and SnapEDA. Usually not worth your time IME.

[VEGETA]

Are you sure your footprint is correct? In the picture it appears that the pads in x-direction have more distance to each other than the pads in y-direction.

well I have used many stuff from them but this was the first like this... and what makes me angry and disappointed is that TI themselves post this link in their own website. I wonder how could such a huge mistake pass through TI.
I downloaded it directly from TI, the link is via Ultralibrarian. Downloaded it again now to verify and it was the same one as I used.

I personally do not trust stuff from Ultralibrarian and SnapEDA. Usually not worth your time IME.

[wraper]

But you have too narrow solder resist bridges again. Reduce the gap between pads and solder mask.

[ataradov]

Thin outline around the pad is copper clearance, not solder mask. Solder mask is not shown here.

[VEGETA]

But you have too narrow solder resist bridges again. Reduce the gap between pads and solder mask.

Check the attached image from an online gerber viewer (not on my device right now). it shows the solder mask.

what you saw there in the previous image was for clearance not anything else.

To my surprise, pcbway doubled the board price because of using 0.2 minimum hole size rather than 0.3mm. I am not really sure what that is, but I never changed any hole or via size according to my memory. still waiting their reply.

and BTW, if I want to make say 100 of them and put them on say 5 panels or so... will that reduce the price to a noticeable amount?

[Zoli]

...
To my surprise, pcbway doubled the board price because of using 0.2 minimum hole size rather than 0.3mm. I am not really sure what that is, but I never changed any hole or via size according to my memory. still waiting their reply.
...

The thermal vias are 0.2mm.

[VEGETA]

...
To my surprise, pcbway doubled the board price because of using 0.2 minimum hole size rather than 0.3mm. I am not really sure what that is, but I never changed any hole or via size according to my memory. still waiting their reply.
...

The thermal vias are 0.2mm.

yes I figured this out earlier on and I just fixed it. made the holes of the newly chosen kicad footprint as 0.3mm for hole and 0.6 for pad. now waiting their response.

[ataradov]

To my surprise, pcbway doubled the board price because of using 0.2 minimum hole size rather than 0.3mm. I am not really sure what that is, but I never changed any hole or via size according to my memory. still waiting their reply.

Check the actual hole sizes. If you have any that are less than 0.3 mm, then you will be charged more. There is no need to wait for them.

EDIT: I see this is due to the footprint. I personally never use those footprints with embedded holes. It is not that hard to add a few vias that match your design on a PCB level. I also don't see why QFN-16 would need 9 vias. That's overkill.

and BTW, if I want to make say 100 of them and put them on say 5 panels or so... will that reduce the price to a noticeable amount?

You can do the online quote thing for this scenario and know the price instantly. $5 does not apply to large quantities, so the price depends on the board size and complexity. You can't extrapolate from $5 without knowing the details.

[VEGETA]

Looks like it went fine.

However, they got another question about those 9 through hole thermal vias. they want to know if they should cover them with resin or not. I told them not to, because I want good soldering connection to the thermal pad of the IC. is this correct?

they also mentioned putting resin in them will, you guessed it, increase cost..

[wraper]

Plugging vias prevent from solder sucking. However if vias are tented on opposite PCB side it's not a big issue, you just need to use a bit more solder paste on center pad.

[VEGETA]

Plugging vias prevent from solder sucking. However if vias are tented on opposite PCB side it's not a big issue, you just need to use a bit more solder paste on center pad.

they are not covered from any side and I don't require it to be so.

what dangers can this have? the vias are 0.3mm hole and 0.6mm pad size, 9 of them on 2.7x2.7 thermal pad which are all ground connections.

the 9 thermal vias connect the main regulator to the bottom layer huge ground pin. it is necessary to have nice connection between them and the IC.

check the attached picture that they sent, looks like it is the vias and solder paste layer.

[wraper]

Plugging vias prevent from solder sucking. However if vias are tented on opposite PCB side it's not a big issue, you just need to use a bit more solder paste on center pad.

they are not covered from any side and I don't require it to be so.

what dangers can this have?

All of the solder will flow to the bottom side through vias and barely any will remain between the chip and PCB. As chip will be pulled towards PCB by surface tension, solder from under the terminals will be squeezed out too and you may have bulging solder balls around terminals.

[VEGETA]

Plugging vias prevent from solder sucking. However if vias are tented on opposite PCB side it's not a big issue, you just need to use a bit more solder paste on center pad.

they are not covered from any side and I don't require it to be so.

what dangers can this have?

All of the solder will flow to the bottom side through vias and barely any will remain between the chip and PCB. As chip will be pulled towards PCB by surface tension, solder from under the terminals will be squeezed out too and you may have bulging solder balls around terminals.

so what to do in such cases? do all people tint or fill the vias all the times?

I mean, does filling them make solder conductivity less to the IC pad?

I will ask them about filling material and their prices to see.

[thm_w]

I always tent unless:
- want the ability to hand solder the QFN, by putting solder on top side, then put chip, then heating from bottom side with iron (time intensive)
- want extra thermal capability by adding solder to the vias (probably not a huge difference)

I wouldn't bother with filling, and you don't need to ask, the quote page gives ~$120 more for 2 layer plugged vias.

[VEGETA]

I always tent unless:
- want the ability to hand solder the QFN, by putting solder on top side, then put chip, then heating from bottom side with iron (time intensive)
- want extra thermal capability by adding solder to the vias (probably not a huge difference)

I wouldn't bother with filling, and you don't need to ask, the quote page gives ~$120 more for 2 layer plugged vias.

by tenting you mean cover them with solder mask? this won't be good here since they are vias in a pad situation. I need the good contact between the pad of the IC and the smt pad (with its vias).

is there a solution to fill but to keep the surface of the via copper exposed and flat? so that it gets soldered nicely and give good conductance? please check the image of the pad above.

the entire quote for assembly + board + component is about 107$. will filling add an extra 120$ for it??

Also, can not filling really make performance worse? or degrade soldering quality of the pad? I gave them instruction to put more solder paste and make sure soldering is good.

[thm_w]

Tenting only on the non-component side, as wraper explained.
You can use their quote page, it adds $120: https://www.pcbway.com/orderonline.aspx

[VEGETA]

they mentioned that the vias will plated. does this mean copper? and that would make good connection to IC thermal pad?

I mean should I use the filling or just go without it? having good connection is important since this is a dual buck converter which will supply 3 amps and 0.5 amps continuously. It has the thermal pad as ground and it is the only direct connection to bottom layer ground plain.

[SiliconWizard]

What's the pitch of this QFN? (Sorry if I missed it.)

Only high-spec (and pricy) fabs manage to put soldermask between pads of fine-pitch parts, and that's usually pretty expensive.
IME, no soldermask between pads is not a problem (as long as the assembly fab is not a dead cow) for pitches > 0.5mm. It can get tricky for <= 0.5mm. 0.4mm being usually the spot where things get really problematic and start requiring manual touch-ups.

[julian1]

Is this for a prototype that is hand soldered? Or a production run with many boards? For a prototype you can solder the qfn, and then desolder it to inspect and verify adequate solder coverage of the gnd pad.   

For reference, I use 4 or 5 vias for small qfn, and never had a problem.

If the via coverage area to pad surface area ratio is high (eg. maybe 50%) then I believe tenting becomes more important (eg. via-in-pad for fpga, or high-density vias for heatsinking), to prevent the vias sucking solder away from the joint. 

In the worst case and for a prototype, you can probably just smear wet epoxy to the back-side, and plug the vias yourself.

[VEGETA]

What's the pitch of this QFN? (Sorry if I missed it.)

Only high-spec (and pricy) fabs manage to put soldermask between pads of fine-pitch parts, and that's usually pretty expensive.
IME, no soldermask between pads is not a problem (as long as the assembly fab is not a dead cow) for pitches > 0.5mm. It can get tricky for <= 0.5mm. 0.4mm being usually the spot where things get really problematic and start requiring manual touch-ups.

soldermask bridge issue has been solved now, the used footprint was wrong despite being from TI.

right now the biggest issue is to fill the vias or not.

please see images above about the footprint with the thermal vias. all of those 9 vias couples the ic to bottom ground plain... top ground plain cannot reach the ic.

Is this for a prototype that is hand soldered?

this is a prototype but will be fully assembled by factory. it is expected to work, so will be the production design.

it is a via-in-pad situation, and i require good solder connection to the ic thermal pad which is also GND.

can the remaining space really take care of it if i tented or filled them?

the manufacturer tells me they will be filled with risen and plated. plated means copper = good connection. but later on she tells me it won't be conductive surface so go figure.

the thermal pad (GND) area is 2.7x2.7cm, and it has 9 vias (0.3mm hole, 0.6mm pad)

[julian1]

If you are price sensitive, then forgo the tenting process. Desolder the part when you receive the prototype, and validate. If you are not-price sensitive, then manufacture it both ways and evaluate.

the thermal pad (GND) area is 2.7x2.7cm, and it has 9 vias (0.3mm hole, 0.6mm pad)

I don't see a small number of vias like that, sucking much solder out of the joint and causing a problem. However there may be an issue that for higher thermal and current handling you ideally want more vias. Does the part datasheet provide guidance?

[wraper]

I don't see a small number of vias like that, sucking much solder out of the joint and causing a problem.

For such a small chip even single via can suck all of the solder if there is enough of exposed copper on the other side to receive all of it.

[julian1]

Dave's video, might help give you a sense of how vias can suck the solder away from the joint. In this case lots of vias used under a power mosfet for power/heat dissipation.


https://youtu.be/pKX50E_14MQ?t=2775

[wraper]

This video, might help give you a sense of how vias can suck the solder away from the joint. In this case lots of vias used under a power mosfet for power/heat dissipation.

https://youtu.be/pKX50E_14MQ?t=2775

For power MOSFETs like that (D2PAK, DPAK package) it's much less of a problem since soldering of the tab does not significantly affect soldering of the terminals. For QFN on other hand it's a very serious factor you need to consider, since it can completely screw soldering quality, cause solder bridging and other nasty things.

[VEGETA]

here is the attached image.  thermal pad is 2.7x2.7mm not cm, sorry for this!



9 vias like that was recommended by the official datasheet: https://www.ti.com/lit/ds/symlink/tps54394.pdf in page 26.

I also attached solder paste layer image, you can see some if it on top of some vias. my vias are larger than datasheet because <0.3mm will require expensive drill

[julian1]

Yes, I think defer to Wraper's experience to rule out issues around automated assembly. 

[VEGETA]

Yes, I think defer to Wraper's experience to rule out issues around automated assembly.

do what is the best solution here? redistribute vias to outside and leave the inside just the pad and then adjust the solder paste to not cover the vias??

removing the middle via maybe can do that? but even though, tent\fill or not?

[julian1]

No. Follow the datasheet, and fill the vias, to rule out issues.

I have got aways got away without filling for qfn, but I hand solder, and have lots of control over the amount of paste, can rework etc. That's a different scenario from manufacturing.

[VEGETA]

No. Follow the datasheet, and fill the vias, to rule out issues.

I have got aways got away without filling for qfn, but I hand solder, and have lots of control over the amount of paste, can rework etc. That's a different scenario from manufacturing.

well, in your experience, for my particular state and footprint... can filling them affect solder quality and thermal\electrical firmness between pad and ic? since this is all care about. I don't want the 9 vias to make the remaining area not suitable or so little touching to the IC and therefore no good electrical signal.

the other 2 ground pins have 1 via each and it won't be enough to put the current imo. but on the bright side, these 2 ground pins are firmly connected to the big ground pad which has the vias

[julian1]

  can filling them affect solder quality and thermal\electrical firmness between pad and ic? since this is all care about. I don't want the 9 vias to make the remaining area not suitable or so little touching to the IC and therefore no good electrical signal.

No, it's the other way around. Not filling them, risks the solder being pulled into the vias from capillary action, which creates a bad solder joint with poor electrical and thermal properties. 

[nctnico]

  can filling them affect solder quality and thermal\electrical firmness between pad and ic? since this is all care about. I don't want the 9 vias to make the remaining area not suitable or so little touching to the IC and therefore no good electrical signal.

No, it's the other way around. Not filling them, risks the solder being pulled into the vias from capillary action, which creates a bad solder joint with poor electrical and thermal properties.

Lead free solder is typically not prone to wicking away from under a chip when using small holes (like 0.4mm vias). Or put differently: I have had a lot (thousands) of boards produced with small vias under QFNs and I have yet to see a board where the solder has reached the other end of the board.

[VEGETA]

so my vias with hole of 0.3mm will never leak or have any risk of bad solder joint? well, the pcbway person was the one who raised the question to me, i never knew this much about vias being filled or so.

>> not filling them:

jullian, I think now I understand the risk of not filling them, but nctnico seems to have the opinion and testing experience that such 0.3mm vias will never pose such risks.

however, my question was about also the soldering and electrical\thermal performance of the IC thermal pad if I used the filling... and ofc because the filled vias will be covered and thus will be 9 circles of no soldering area. this is what concerns me.

my vias are 0.3mm hole and 0.6mm diameter, meaning about 0.15mm of via copper all around it... so, if they are filled with risen, will the via copper itself be covered as well?

if it will not be covered, then it will be no problem! since it will get connected to other pad area with solder... my concern if it will be covered, then we will have 9x0.6mm circles of "no solder" breaking the area which may hinder the performance.

what is your experience on this?

the pcbway representative does not answer questions in details.

[ataradov]

Nobody would be able to answer definitely if it will work fir you or not.  It all depends on the specifics of the assembly process, like temperature profile and solder paste used.

If you are making small runs, don't worry about it too much unless you actually see the issue, in which case you will have to make adjustments.

If you are making huge production runs, plug the holes, don't risk it. 

I definitely seen 0.3 mm holes wick the solder through during manual rework when there were no issues during the automated assembly. Obviously manual rework does not follow any standard temperature profiles and is likely huger temperature than a regular reflow process.

[VEGETA]

Nobody would be able to answer definitely if it will work fir you or not.  It all depends on the specifics of the assembly process, like temperature profile and solder paste used.

If you are making small runs, don't worry about it too much unless you actually see the issue, in which case you will have to make adjustments.

If you are making huge production runs, plug the holes, don't risk it.

well, for plugging the holes... my holes are 0.3mm and the entire via is 0.6mm, so the via copper is about 0.15mm all around. if they are risen filled (or any fill), will the filling and covering using non-conductive material be on just the 0.3mm or the non-conductive material will be the entire 0.6mm area?

if only the 0.3mm then yes, it will be no problem for any performance and so on.

how can we be sure? the pcbway rep says via surface will be plated but also non-conductive, she does not give much details.

[ataradov]

The entire via does not have to be 0.6 mm, it is all copper anyway, it can be anything. Plugged vias and vias just covered with solder mask are very different. Full plugging is generally more expensive. And for simply covered vias - pick a diameter that your board manufacturer can reliably produce. They will not be able to just cover 0.3 mm, since that't the hole. Solder mask needs something to hold on to.

You are overthinking this. Just make the board with holes open and see what happens.

[VEGETA]

The entire via does not have to be 0.6 mm, it is all copper anyway, it can be anything. Plugged vias and vias just covered with solder mask are very different. Full plugging is generally more expensive. And for simply covered vias - pick a diameter that your board manufacturer can reliably produce. They will not be able to just cover 0.3 mm, since that't the hole. Solder mask needs something to hold on to.

You are overthinking this. Just make the board with holes open and see what happens.

first my holes were 0.2mm and they charged me twice because of using a fancy drill, now changed it to 0.3mm.

assuming the vias covered with risen, it will be 9x0.6mm in that area. will the other remaining area be enough for the ic to have best performance? i mean those 9 filled and covered vias won't affect it/??

i worry because if proto board worked with no covering, then for some reason didn't work well for production... i will be losing a lot of money

[Bud]

vias will be covered and thus will be 9 circles of no soldering area. this is what concerns me.

my vias are 0.3mm hole and 0.6mm diameter, meaning about 0.15mm of via copper all around it... so, if they are filled with risen, will the via copper itself be covered as well?

Remove 4 corner vias and tent the remaining ones, problem solved.

[VEGETA]

vias will be covered and thus will be 9 circles of no soldering area. this is what concerns me.

my vias are 0.3mm hole and 0.6mm diameter, meaning about 0.15mm of via copper all around it... so, if they are filled with risen, will the via copper itself be covered as well?

Remove 4 corner vias and tent the remaining ones, problem solved.

aha so the remaining ones will be enough to properly couple the IC to the internal bottom layer ground plain and have good thermal performance... at say 4 amps total load?

[Bud]

If max current is a concern you can adjust the remaining via size to compensate for loss of removed vias stem surface area.

[wraper]

Lead free solder is typically not prone to wicking away from under a chip when using small holes (like 0.4mm vias). Or put differently: I have had a lot (thousands) of boards produced with small vias under QFNs and I have yet to see a board where the solder has reached the other end of the board.

IME it wicks to other side with 0.3mm vias if there is exposed copper to receive that solder. The best is plugging the vias but it costs a lot. On the other hand tenting on other side is completely free and usually is good enough. Sometimes vias get tented on top side instead of expensive plugging, right under the chip to completely eliminate the wicking. However it's only applicable for larger chips if vias are not populated densely.

[VEGETA]

They gave me the price for plugging with risen, it is 240$!!! no way I am paying that. I wonder if I ordered 100 boards, what will the price be for plugging xD

however, does removing the 4 cornered vias help eliminate this? i mean they are the only ones with solder paste above them.

I am not familiar of how to tent one side of a via in kicad... tenting them in both sides may eliminate the issue but maybe won't be firm soldering


what to do now?

[ataradov]

however, does removing the 4 cornered vias help eliminate this? i mean they are the only ones with solder paste above them.

No, the solder will flow. But that's another thing you can control. If in practice it turns out that vias capture some of the solder, you can increase the openings in the stencil, basically compensating for the lost solder.

what to do now?

Don't overthink it, just order the boards with the simplest and cheapest process and see how the soldering goes.

[VEGETA]

I think I will order them without filling for now.

I wanted something to be fully working and guaranteed for production. I don't want a good prototype then when it comes to production it would not work or some units do not work properly...etc since I cannot test all units.

for now I will order them without filling... can you suggest something for future? I mean for production, covering the vias will be relatively affordable so yes i can fill them. but gotta guarantee if they are filled, the soldering, electrical, thermal performance to be good.

For example, I can increase the 4 solder paste areas to be more... maybe slightly more than the footprint? please check the attached image for illustration. 2 images for 2 suggestions.

[ataradov]

I wanted something to be fully working and guaranteed for production.

Everybody wants that, but you can't have this in most cases on the first try. That's why you do prototypes - to figure out what can go wrong. And then before mass production you do small engineering runs to figure out what may go wrong during mass production.

PCB assembly itself is not a guaranteed process that just works 100% of the time, it may need to be adjusted for a specific board. Most of the time things just work, but sometimes they don't.  And only assembly house will be able to tell you their confidence level that your specific design will not have issues.

I don't want a good prototype then when it comes to production it would not work or some units do not work properly...etc since I cannot test all units.

can you suggest something for future?

You can just see how evaluation goes and do nothing if it seems to work. You can also see if thermal performance is an issue in your case and if you really need all those vias.

For example, I can increase the 4 solder paste areas to be more... maybe slightly more than the footprint?

All of this is tuned during the engineering runs. But generally it is not a great idea to just add more solder. The issue here is that if you don't explicitly plug the holes, they may still get plugged at random, so the amount of solder they will take will vary.

None of this is exact science and you have to deal with issues as they come up from design to design. Or commit to the most expensive manufacturing process. It is up to you to estimate what will cost more.

Also, the prices for big orders would drop, of course, so may be having smaller holes or plugged vias would be acceptable. You need to get quotes for the actual quantities you will want, don't try to guess based on the prototype prices.

Also, without prototypes, what makes you sure your design is even functional? You already almost made the boards with the wrong footprint. What makes you so sure that the reset of the footprints are correct?

You will have to build something to do the tests, and that's a good opportunity to observe how the boards behave during assembly. 

[VEGETA]

your suggestion seemed ok with me. I mean using smaller holes and plugging them then use good amount of solder to fully seal and solder the IC... all this durring manufacturing the production units.

if this batch of just 2 assembled boards worked, which it will unless something majorly wrong is there.... i will make another small batch of say 5-10 assembled boards using the 0.2mm hole vias (exactly the same as datasheet) and plugged holes.

if that also worked, then i will use it for all production in the future.

i just wanted to do one iteration of prototypes instead of 2, but as you said, can't get it right the first go.

[westfw]

I don't know how much good those "thermal vias" are going to do without a substantially more "solid" ground plane on the other side of the PCB.  A lot of those SMPS chips seem to assume a 4-layer board with the bottom layer being almost solid ground plane.

For maximum heat sinking, you WANT the vias to get filled with solder - a solder-filled via should be significantly more thermally conductive than a via with just plating or non-metallic fill.  I don't know how to balance that with the "wicking" problem that others are concerned about :-(

[VEGETA]

I don't know how much good those "thermal vias" are going to do without a substantially more "solid" ground plane on the other side of the PCB.  A lot of those SMPS chips seem to assume a 4-layer board with the bottom layer being almost solid ground plane.

For maximum heat sinking, you WANT the vias to get filled with solder - a solder-filled via should be significantly more thermally conductive than a via with just plating or non-metallic fill.  I don't know how to balance that with the "wicking" problem that others are concerned about :-(

the bottom layer is all ground plain, which is what you mentioned here.

the boards are on route to me, without resin filling. and from picture it looks like there is no wicking or spillage.

balance is what we do here xD  so kindly mention you balancing theory 

[VEGETA]

Hello

the boards arrived in Amman Jordan but will need time to get to me, will examine then but from pictures sent by manufacturer there does not seem to be any leakage.

However, I asked for a quotation of just PCB manufacturing using 3 options and here are the results:

1- via on pad without filling (our current options):
5 pieces     = 44.14 USD.
20 pieces   = 53.65 USD.
100 pieces = 93.81 USD.

2- via on pad with copper filling (what is considered to be the best):
5 pieces     = 431.09 USD.
20 pieces   = 431.09 USD.
100 pieces = 486.61 USD.

3- via on pad with resin filling:
5 pieces     = 268.79 USD.
20 pieces   = 268.79 USD.
100 pieces = 349.94 USD.


huge price increase as seen! components + assembly for 20 boards is about 500$ while it is about 1400$ for 100 boards. selling this for 50$ seems ok if I choose no filling and 100 quantity as it seems, especially that there is customs which is a giant monster here!

for 100 quantity: without filling = ~1500$ -> = 15$ per one unit + 5$ per unit as approx. customs = 20$ per unit total. sold for 50$ is kinda ok. however going for filling will make it harder. resin will make it about 23$ per unit and copper will make it more than 25$.

for 20 quantity: without filling = ~550$ -> ~35$ per unit including customs...

is 20 quantity as above good for first batch?

what will you do if you are in this situation?


if i got them as non filled, then checked the boards manually to remove the leaked solder will it be ok? or maybe reflow it from the bottom using soldering iron.

for your kind suggestions.

[ataradov]

For small quantities like this, I'd go with the cheapest option. If something fails on a couple units, you can always manually rework them. The real issue starts when you need to make 1000+ of them.

[VEGETA]

For small quantities like this, I'd go with the cheapest option. If something fails on a couple units, you can always manually rework them. The real issue starts when you need to make 1000+ of them.

so you did some manual reworking in the past? what about my suggested reworking by soldering iron is it good enough.

I don't think I will ever make +1000 at once, at least not in foreseeable future. actually, for 100 it is kinda ok financially, just not good enough for making good profit margin. I assume 1000 or more is going to be really negligible loss of money if we choose copper filling.

[ataradov]

What you will have to do depends on the nature of the issues you will get. There is a high chance that you won't get any issues.

Don't overthink it. You have the hardware on a way, just wait and see.

[VEGETA]

Hello all, as I mentioned here: https://www.eevblog.com/forum/projects/my-psu-design-ripple-and-noise-with-picture-measurements/msg4518794/#msg4518794

the project works as intended and there were no problems in spillage and so on, actually the holes are extremely small and I think it is kinda impossible for solder to spill from there... very narrow.

the 3.3v rail has nice clean 5-10mv p-p total noise\ripple... but the 5v rail is significantly bad at about 40mv p-p which is shocking to me!

I am trying to know the root problem as seen in my last post there, which I suspect it is due to long travel of the 5v signal then routed by a via under 3.3v ferrite bead.

for your help if you can.

I was VERY close to finally wrap this and start production... so hyped