Power puddle or not power puddle.

[paulca]

I've been watching quite a few of "Phil's Lab" videos on YT.  He spends a lot of time designing and reviewing "Mixed signal" boards.  Usually MCU boards with ADC/DAC or RF sections.

I've been trying to follow some of his best practices with breaking the schematic up into functional blocks,  well labelled and isolated etc.

On PCB layout and routing I tend to do a trash layout, learn a lot of things and make a mess.  Then I start fresh with what I've learnt and make a mechanically oversized version.  Then by refining and becoming more and more confident in the positions of components I start to move them together and, if possible, into neat grids/rows etc.   Usually the board shrinks by a factor of 4 in this step.   This is where I am in my design so far and I've been trying to go around the routing and adding "best practices" here and there.

Power puddling.

Phil seems to add copper pours around concentration of power, such as around the voltage regulator, bulk caps and main MCU VDD pins etc. 

If I understand correctly adding "power plains or puddles" is basically using the PCB capacitance to your advantage, by creating a ground plane with a power plane above you are effectively creating board capacitance.  The wider copper should create lower resistance too of course.

It's the later point that makes me question just how valid my attempts have been.

Example:
USB Micro B SMD connector.  ALL of the power for the board comes in here.  I'm targeting 200mA MAX and probably running mostly around 100mA.  5V supplies a 3v3 LDO for the MCUs and the LED backlight in the TFT.

The thing is, that power comes in on 2 single pins on the USB footpint.  The maximum track size for DRC is 0.25mm.  I "can" squeeze a 0.5mm track in but I get DRC warnings as they are too close to the mechanical pins.  These pins are GND and VBUS.  So I have this massive ground plane and an attempt at a power plane, but ultimately VBUS is connected by a single 0.25mm link to the pin and GND is connected by a 0.25mm track stitched with 4 vias to the ground plane.

Those tiny little links just seem to make the whole idea a bit pointless.

The board has no analogue signals.  It's 100-200mA mickey mouse hobby project with 2xMCUs and a TFT.  Is it worth wasting time on power puddling or just run my VCC/VDD around the board as I please and spend my effort making the decoupling caps and xtal layouts nice?

[capt bullshot]

I've seen these "power puddles" too, with professional designers doing them.
Well, professional in the meaning of "they're doing layouts all the time, but they aren't electronics or EMI experts". They just do the layout according to some instructions they get from some engineers.

Anyway, IMO this is kind of a religious thing, some believe it helps through capacitance and because any power plane is a good thing, other say its bad EMC wise, because the puddles might turn into antennas at some frequency.
My personal way would be: One big fat ground plane, no splits in the plane, in case there's room on other layers, extend the plane here. Capacitors do the power decoupling job, assuming they're placed and routed reasonably.

One can ignore DRC, or tell PCB designers to ignore DRC rules locally. Too narrow tracks for power at least look bad IMO.

[thm_w]

The board has no analogue signals.  It's 100-200mA mickey mouse hobby project with 2xMCUs and a TFT.  Is it worth wasting time on power puddling or just run my VCC/VDD around the board as I please and spend my effort making the decoupling caps and xtal layouts nice?

Its not worth spending time on that, for this design, no. That said, if you drop a power plane down, it can make your life easier as now you don't have to wire all those vcc connections manually.

For the thin trace, its OK to have a thin trace coming off a pin and then neck it out wider once you have the space to. But again, your CAD software can probably already do this for you when you drop the plane down.

[paulca]

Yes a friend was pushing me to go 4 layer.  I said I didn't need 4 layers for such a simple board, but he insisted it would make things so much easier.

I tried it, using the top layer as power plain, split with VBUS, VCC puddles around the power supply area and then the rest of the board VDD.  The trouble is the DRC's got me again.  If I set my VDD net class to have 0.5mm tracks/via reliefs etc.  Then it doesn't actually connect the MCU pins to the power plane as their DRC maximum is lower than 0.5mm.  So it leaves all the nets on the MCU disconnected.  If I reduce the DRC and gaps it will attach them, but that means the DRC/gaps etc are removed "across the board" and I don't want that.  I'm sure it can be tuned and I can check the PCB Fab limitations and push things closer to the line to get what I want...

However I've decided to go back to 2 layer.  I can get rid of VCC entirely, I was using it to run the TFT backlight, but the 3.3 reg has more than enough power to handle that off VDD.

That and the realisation the best form-factor for my PCB would be a match for the TFT PCB and use the existing pin headers on either end to join the two boards together in a sandwich.  This should make the case mechanics a lot easier.  Also expands my board area quite a bit and so I don't have to fiddle around so much in cramped spaces... or go down to 0605s.

The other factor to consider is this will be "home soldered".  I want to try hot plate (frying pan of sand and a thermocouple), but might chicken out and go with known air soldering, finished off by hand.

[Geoff-AU]

For the thin trace, its OK to have a thin trace coming off a pin and then neck it out wider once you have the space to. But again, your CAD software can probably already do this for you when you drop the plane down.

Yep.  Electrically, having a thin trace for as short a distance as possible and necking out simply means you minimise voltage drop.  Thermally, the pin will provide a fair bit of heatsinking so a short length of trace will wick heat into the pin, a longer length of trace will get hot if it's running high current.  Necking it out wider solves both issues.  For 200mA it's not really an issue though.

Power puddles using distributed capacitance between planes works best when the planes are close (prepreg rather than core between layers) and only relevant for high speed design.  Capacitive pours are only giving you a few picofarads (eg a 2 layer board 1.5mm core layer with 3x3cm pours, you have about 5pF).  If you do a 4-layer board and put planes inside then you might have 1mm of core worst case, and 5x5cm planes will have 22pF.

[paulca]

Funny enough for my Cs (capacitance stray) on the XTals, I put my finger in the air, made a face and picked 5pf.  In fairness I've seen about half a dozen people do the same, wave off stray capacitance on the board as about 5pf.

I suppose if you are deailing with a modern CPU at 5.0Ghz+ and pulling 200A that 5pf and whether it's 5 or 5.5 becomes an issue.