problem/question re bypass cap for THT device on four layer board

[legrady]

On a two-layer board, I would place a bypass capacitor next to an IC and run power traces to the cap and on to the IC power pin.

Now that I'm using four layers, I can do the same with SMD devices. Now I want to use a PT2399 digital delay chip, which is only available as a 16-pin dip. So the power pin is 'drinking' from the power plane, with the 100nF capacitor 'nearby', rather than the capacitor literally being a local trough for the IC to 'drink' from. Does this matter?

Should I have a trace from the SMD capacitor to the power pin? Or have the capacitor connect to the power plane using a via, next to the power plane? Or am I OCD?

Tom

[coppercone2]

its not OCD its a careful balance of noise performance and possibly reliability (too much stuff too close together)



https://resources.altium.com/p/bypass-and-decoupling-capacitor-placement-guidelines

They generally seem to recommend lower inductance solutions, but I bet there are special cases.

Typically people advocate low inductance. But as far as how much of that is just parroting (since inductance is the most obvious), its hard to tell.

i.e.
https://www.protoexpress.com/blog/decoupling-capacitor-placement-guidelines-pcb-design/

[thm_w]

vias will have some inductance (maybe 2nH), will it matter for a PT2399? no. Is it optimal? no.

https://www.protoexpress.com/blog/decoupling-capacitor-use/
https://www.protoexpress.com/blog/decoupling-capacitor-placement-guidelines-pcb-design/

[Zoli]

...
Now I want to use a PT2399 digital delay chip, which is only available as a 16-pin dip.
...

LCSC has SO16 and SO16 wide:
https://www.lcsc.com/product-detail/C126407.html
https://www.lcsc.com/product-detail/C85146.html

[legrady]

Thanks for the advice about cap placement. Obviously, the SMD version of the PT2399 is the best solution! But there will be other cases.

Tom