Author Topic: QFN land pattern standard?  (Read 2552 times)

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Offline TheCometTopic starter

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QFN land pattern standard?
« on: March 03, 2016, 05:07:56 pm »
Is there a standard for QFN package land patterns? I've noticed some ICs have a pitch of 0.65mm, others have a pitch of 0.5mm and both claim to be a QFN package. This is super confusing because so far my library of land patterns hasn't been making any distinctions between pitches.

0.65mm (Page 15) http://www.yamar.com/datasheet/DS-SIG60.pdf
0.50mm (Page 21) http://cds.linear.com/docs/en/datasheet/37411ff.pdf
0.50mm (Page 38)
http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf
« Last Edit: March 03, 2016, 05:12:45 pm by TheComet »
 

Offline DeepOrange

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Re: QFN land pattern standard?
« Reply #1 on: March 03, 2016, 05:47:13 pm »
Perhaps this JEDEC PUBLICATION 95, DESIGN REGISTRATION 4.24 will answer your question:
www.jedec.org/sites/default/files/docs/DRegistration4-24A.pdf (see attached)
 

Offline T3sl4co1l

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Re: QFN land pattern standard?
« Reply #2 on: March 03, 2016, 06:34:26 pm »
Whatever it is, doesn't matter all that much -- as long as you follow the drawing, and recommendations, preferably from a PCB assembler that knows what solders best.  IPC-7351B is freely available and a good start for how to dimension most footprints.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline m98

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Re: QFN land pattern standard?
« Reply #3 on: March 08, 2016, 06:14:52 pm »
I just always use the recommended footprint from the component datasheet. Too many come in non-standardized, vendor specific packages, who sometimes only differ to the standard in one small but important detail.
 


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