Question about SMT ground planes - 10MHz SPI

[kcbanner]

So I haven't done a primarily SMT PCB before, but I am forced to with this design because the atmega32u4 only comes in the TQFP package. The design is fairly simple, just connection to two OLED screens via SPI, one at 5v and one at 3.3v, served through 4050 as a level shifter. The SPI bus ideally I would be running at 10MHz but it might be closer to 5Mhz or even 2.5Mhz depending on how things turn out. With the design breadboarded with wires/probes everywhere I'm running it at 2.5MHz. The 3.3v display is connected directly to the PCB via the 2x8 header, and the 5v display via a short (10cm) ribbon cable.

I have a first pass done on my layout, with gnd on the top layer and +5v on the bottom. I'm a bit worried about some areas, to the right of U2 there is a part of the gnd plane that is only connected through a pin of the atmega. This doesn't seem great to me so I'm thinking I should take another pass with the layout and try to open up a few more areas. I'm wondering if I need to be concerned with this? Or if I should switch the gnd plane to the bottom as I've read on the forum that you should run higher speed tracks over a gnd plane.

All of my designs up until now have been lower speed through hole, so I'm a bit lost in this area.

[cowana]

The key thing to think about is current loops - for every high speed rising edge on the SPI bus, there will be an equal current pulse flowing through the ground trace between the driver and display. Try visualising where these loops will go (including flowing through the ground trace) - you want to try and make sure the ground is a good clear path.

If you're worried about having poorly connected areas of the plane, GND on both the top and bottom might make more sense, as you can then stitch them together with static vias.

[PCB.Wiz]

So I haven't done a primarily SMT PCB before..

I have a first pass done on my layout, with gnd on the top layer and +5v on the bottom. I'm a bit worried about some areas, to the right of U2 there is a part of the gnd plane that is only connected through a pin of the atmega. This doesn't seem great to me so I'm thinking I should take another pass with the layout and try to open up a few more areas. I'm wondering if I need to be concerned with this? Or if I should switch the gnd plane to the bottom as I've read on the forum that you should run higher speed tracks over a gnd plane.

What you have so far looks ok, but if you want lowest overall GND plane impedance, then certainly try a design-fork to GND on lower side, as you are thinking is a good idea.
See how that routes and pours and compare the two. (usually you have a small local GND under the QFP on top & maybe to xtal too )

You can push traces/vias to give more GND at the expense of less +5V, and you can also add short stitching traces to the other side, to avoid long paths to isolated fingers.

[kcbanner]

The key thing to think about is current loops - for every high speed rising edge on the SPI bus, there will be an equal current pulse flowing through the ground trace between the driver and display. Try visualising where these loops will go (including flowing through the ground trace) - you want to try and make sure the ground is a good clear path.

This is good to know. Maybe I should print this out and get out the highlighter and figure out where these loops are.

See how that routes and pours and compare the two. (usually you have a small local GND under the QFP on top & maybe to xtal too )

Cool, I'll give this a try.

Thanks for the feedback!

[KE5FX]

Main thing with high-speed SPI is source termination.  I'd suggest series resistors close to the output driver pins.  You can always put zero-ohm parts in if you don't need them.

[vltr]

It's not what you asked about, but it looks to me in your render that C2 is shorted. 

[kcbanner]

It's not what you asked about, but it looks to me in your render that C2 is shorted.

That's actually the one end of C5 and C2. They are side by side (note the green lines below).

The boards turned out nicely (see post here: https://hackaday.io/project/17601-f16-desktop-cockpit/log/51046-usb-ded-ffi). The SPI signals work great even with a 10cm ribbon cable between the board and LCD.

[timb]

Personally, I'd use the top *and* bottom as a GND plane, with lots of via stitching between sides and then directly route 5V/3V3 to the places it needs to go. Just use a large enough trace to avoid a voltage drop and you should be good.

Also, a good way to visualize your current flow is to print a copy of your layout out then use a ruler and pencil to to draw a straight line from each component's ground pin to the point it comes in on the board. If it crosses a lot of signals *or* has to go around a bunch of vias or cut up ground pours, you need to re-evaluate the layout.

For signal traces, GND should be able to follow them on the opposite side of the board. So, if your SPI traces are on the top layer and your GND is only also on the top, that's a problem.