Relay Shifter PCB Design Issues

[mblyman89]

Hi all! First time poster here. I having been trying without any success to create a PCB of a circuit I tested on my breadboard, and keep getting unexpected results. I am using two sn74hc595n shift registers with two uln2803apg darlington transistor arrays to interface my raspberry pi with a 12v sainsmart 16 channel relay module. Everything works well on the breadboard, however, after creating the schematic/ PCB in EasyEDA and having JLCPCB manufacture said PCB, I am getting unexpected results with it. Things like relays wont activate, or the wrong relay will activate, or two or more relays will activate when I only asked one to activate. I have tried many different variations of the design hoping to find the right configuration that will achieve the output I desire. I am very new to the electronics world and really don't know what I am doing, but thought the circuit was basic enough that even I could figure it out. I have sorely under estimated the difficulty level (and my capabilities) of this project and am hoping someone can spot the mistakes I have made with my design. My goal is to create simple firework controller. The circuit design allows (supposedly) for multiple PCBs to be connected in series so I can have many outputs to use in my controller. the PCB is connected directly to the relay module via a 2x10 female header block where the PCB is powered by the 5v and ground outputs from the relay module. My PCB is a four layer board with the two inner layers as ground and power planes. I used 5mil traces for the signal connections, and 10mil traces for the power and ground connections. From the Pi to the PCB, I use one ground pin, and four GPIOs to control SDI, SCLK, RCLK, and SCLR. I have the output enable pin of the shift registers tied to ground as I don't need to toggle that pin so the shift registers outputs are always enabled. I am using a .01uF bypass capacitor for each shift register as per the data sheets recommendation. I've uploaded a picture of the schematic and a picture of the PCB design/ layout. The links below point toward the EasyEDA files of said schematic and PCB. Thank you all for helping me! I should be receiving from JLCPCB the design I linked below any day now, so maybe it'll work this time, or maybe I wasted more money jumping the gun again before asking for help. If you want also, I can post the python script I wrote, it's my first time writing a python script too, so it can certainly use some refining I would imagine!

https://easyeda.com/mlyman89/Relay_Shifter_Controller

https://easyeda.com/editor#id=|f4f15e2f8410409e9deb7fc40f12660c|fcd2d4aa40fd49acbed59be7bb4cd230

[S. Petrukhin]

I think you forgot to do the GND bus wiring...

[S. Petrukhin]

Oh, no! You did that on 4 layers... 

[S. Petrukhin]

At what frequency do you transmit the signal to the shift registers? Maybe you should lower the frequency for step-by-step mode and check the download? Maybe you should disconect the load and check on the LEDs? It may very well be that the inductive load interferes with the power supply. After all, the protective diode inside the UNL key does not take over and does not emit self-induction EMF into the atmosphere, but sends it to the power bus. Try to put protection diodes directly in parallel with the load.

I'm not looking for your mistakes, I'm trying to help you find them yourself.  Learn how to test and debug on your own.

[2N3055]

Lookup term "decoupling capacitors".. You have none.  Those two at the edge of the board doesn't count...

[Siwastaja]

Lookup term "decoupling capacitors".. You have none.  Those two at the edge of the board doesn't count...

Why not? Eyeballing it, they are about an inch away. Definitely not ideal, but likely works just fine.

I might use just two as well, I'd just place them between the two ICs so that they would be closer to the power pins.

Depending on how the input is powered, I'd add a high-ESR bulk (electrolytic, for example), though, on the edge of the board (where power comes in).

[daqq]

Why not? Eyeballing it, they are about an inch away. Definitely not ideal, but likely works just fine.

It'll work, but it can work much better. See:

[S. Petrukhin]

Look here: https://oshwlab.com/f33net/relay_shifter_controller_new 

[mblyman89]

Thanks for the advice. I’ve done a lot of reading about capacitors and their different functions. I guess out of ignorance I assumed that .01uF ceramic capacitors are relatively similar. The data sheet doesn’t specify what type of capacitor to use only saying that .01uF is recommended, as well as saying to place said capacitors as close to the chip as possible. Which .01uF capacitor would you recommend I use? Is there a better place to put the two capacitors? Again, this is literally the first time trying to do anything electronics related, and I assumed if I mimicked the breadboard setup, which worked without issue, that the pcb setup would too. I didn’t use a capacitor when bread boarding, and it still worked as intended, so my level of understanding is that of a small child at this point! I do appreciate all the advice thus far, I will try doing some things differently to see if I can get the results I’m looking for.

[mblyman89]

Look here: https://oshwlab.com/f33net/relay_shifter_controller_new 

Oh wow, this is exactly what I’m trying to create. His design is much more complex than I thought it needed to be, yet another indication of my level of ignorance in pcb engineering! Thank you for point me in that direction!

[S. Petrukhin]

Look here: https://oshwlab.com/f33net/relay_shifter_controller_new 

Oh wow, this is exactly what I’m trying to create. His design is much more complex than I thought it needed to be, yet another indication of my level of ignorance in pcb engineering! Thank you for point me in that direction!

I waited a long time for the train, I was bored and decided to make you a design that can be a useful example. This is a 2-layer PCB for $2 - no need for 4 layers.

Please note: the presence of an indication on the Board is certainly not mandatory, but it is very convenient and even fun.

The required capacitors are 0.1uF, not 0.01uF. There are no special requirements for them - ordinary multi-layer ones. You don't have rigid high-frequency regular processes. I think it's not just the capacitors that are the problem.

I didn't look at your design carefully. But pay attention, study how the food is diluted - this is no less important than blocking caps. Dave has some videos on this - I highly recommend watching them. And his other training videos are very good - you will watch without stopping.

Finally: probably not the board design is to blame. You may have made a mistake during installation, some leads may not be soldered or there may be jumpers somewhere, you may have damaged the chips with static electricity.

I recommended you ways to find out the cause, try in quality. To find a reliable result is a very useful experience.

When you review my design, disable the display of the copper polygon - they interfere with viewing.

[S. Petrukhin]

EasyEDA did something inconvenient with open projects. Here's a more convenient link: https://easyeda.com/f33net/relay_shifter_controller_new

[mblyman89]

Can you tell me more about the PE and ground connection on the 3rd capacitor and resistor? Why is the ground symbol a triangle and the PE symbol also a ground looking symbol? As well as the purpose of the big circles in the corners? Thank you so much for making this schematic and PCB example, its really awesome!

[S. Petrukhin]

Can you tell me more about the PE and ground connection on the 3rd capacitor and resistor? Why is the ground symbol a triangle and the PE symbol also a ground looking symbol? As well as the purpose of the big circles in the corners? Thank you so much for making this schematic and PCB example, its really awesome!

I'm sorry, I made a mistake. I dragged this part of the diagram from my project, and I had GND marked differently. I just fixed the circuit diagram.

PE is the ground connected to the chassis. It has no direct contact with the Gnd, but is connected via C3 and R45 so that electrostatic pulses and charges can drain out to PE from circuit. For the operation of the circuit, a large resistor resistance and a small capacitance (there, however, it is necessary to put a high-voltage capacitor) do not affect the operation of the circuit, but for static charges this is a good way. They are also necessary if there is no grounding: so that the PE polygon does not fly in the air, and can, at least, give a charge to the Gnd.

Circles at the corners are holes for fixing. They are metallized to connect the PE pad to the chassis for graunding.
You cann press [3D] on toll bar for view 3D model of PCB.

[mblyman89]

Thank you so much for the design and explanations! I am starting to understand this all, little by little. Much appreciation!

[Siwastaja]

I was commenting to the claim that the two capacitors placed by the OP "do not count". Of course they do, even if suboptimal, it's not catastrophic.

Power decoupling capacitors are chosen by impedance at high frequencies, and that is completely defined by their inductance (capacitance is irrelevant when you satisfy a certain minimum), and further, inductance is completely defined by the total loop area, which is simply defined by package size + layout.

Typical 0.1uF is kind of minimum capacitance. There is no harm done if you have more, say 1uF. More than 0.1uF may also be needed with some ICs like high-current gate drivers.

So choosing these puppies is mostly based on package size, price and availability!

For them to perform optimally, use the smallest package size you can handle, and place it as close to the chip as you can. Underlying idea is to minimize the loop: IC Vcc -- cap Vcc -- cap GND -- IC GND.

This being said, it's not set in stone that you need exactly <5mm loop, and 25mm loop would fail to work. It's all about the internal design, IO edge rates and drive strengths of the ICs involved. Some are fine without any decoupling at all, some require near-perfect design. With typical CMOS logic ICs like this, common practice is to include bypass caps every inch or so. Which is at least almost satisfied by the OP. You don't absolutely need to have one cap per IC, the distance between the caps and ICs is more important.

I would be a bit worried about the idea of using just 0.01uF, though. And of course, while at it, move the caps closer as suggested.

And, high-ESR bulk capacitance is almost always a good idea unless you are 100% sure it won't be needed.

[nctnico]

To the OP: use tpic6c595 or tpic6b595 chips. These have internal protection (thermal + overcurrent) and have the shift register inside. Much easier.

Also check whether you are satisfying the timing and signal level requirements on the SPI bus using an oscilloscope. I recommend to put some small capacitors on the SPI clock line. 47pf to 220pf or so to reduce susceptibility to spikes from the relays switching.

[mblyman89]

Thank you all for the advice and knowledge! I will look into the tpic6c595 chip. Sounds promising.