Calculate Vias size When Connect Power Lines Between Layers

[2X]

Hi,
can I calculate the vias size and the number of vias when I connect power lines between two layers?
I want to connect a power line between top and bottom layer. The width of the trace is 2.5mm.

How many vias I have to place and in what size (each via must have) in order to not increase the resistance at the point of the transition between top and bottom layer?
Also, I am using the Altium Designeer, so if there is any automatic way to create this multiple via pattern (like at the below image) please tell me.



Picture Source:
https://electronics.stackexchange.com/questions/458586/is-one-big-via-better-than-multiple-small-vias-when-changing-power-traces-and-gr

[Doctorandus_P]

Quite often the thickness of tracks is 35um, and the wall thickness of the via "tube" is half that, so approx 17um. From that it's a quite easy calculation to have a similar cross section for the vias as for the tracks.

But the thickness of tracks can both be thicker or thinner, and you have to keep that into account.

[thm_w]

Saturn PCB has a via calculator: https://saturnpcb.com/saturn-pcb-toolkit/
Altium you use tools > via stitching: https://www.altium.com/documentation/altium-designer/via-stitching-via-shielding-pcb

[2X]

If we unwrap the barrel of the via we take a straight PCB track.
So, in order to have a similar cross section of resistance between PCB track and via barrel, then both (via barrel and track) must have the same volume. So how can I combine all these and calculate the volume of the via and track in order to be equal? (or I miss something)

My PCB have thickness 1,6mm and 35um(1oz) copper thickness and via barrel thickness 17um.
The width of the track is 2,5mm.

[tooki]

Saturn PCB has a via calculator: https://saturnpcb.com/saturn-pcb-toolkit/
Altium you use tools > via stitching: https://www.altium.com/documentation/altium-designer/via-stitching-via-shielding-pcb

Via stitching does not do that. It connects copper pours, not tracks.

X2, you’ll have to do it by hand, but it’s easy enough to reproduce.

[2X]

I made some "calculations" and I want to share them with you because maybe I missed something.

[thm_w]

Using the Saturn calculator, assuming via plating of 25um, to calculate maximum current (20C rise):
- First case would be 2.5A * 4 = 10A
- Second case would be 3.6A * 2 = 7.2A

[2X]

With the Saturn PCB with a via 0.8mm the current is ~3.7A and with a via 0.4mm the current is ~2.5A.

Circumference = 3.14 x 0.8mm = 2.512mm

Circumference = 3.14 x 0.4mm = 1.256mm (2.512mm/2=1.256mm)

The 0.4mm via has half (1.256mm) of the circumference from the 0.8mm via (2.512mm), so why doesn't have and half of the current (3.7A/2=1.85A) from the 0.8mm via and instead has 2.5A?

What am I missing in my calculations?

[thm_w]

You can see in your calculator screenshot, resistance is about half for 0.8mm.
P = I²R
If resistance drops by 50% from 0.4mm to 0.8mm, keeping power constant, then current will go up by ~40%.
3.7A / 2.5A = 48%

Why power is about the same, not sure. A lot of these calculations are overly conservative rules that have some relation to reality but are not exact: https://www.signalintegrityjournal.com/articles/1459-vias-are-cooler-than-we-think

As referenced in the above article, internal trace calculations used to derate internal traces, but that was actually completely wrong and now they are no longer derated (in saturn).

[2X]

I used 4 vias 0,4mm because give me 10A instead of 2vias 0,8mm with 7,4A (and this will be OK for me).
Thanks all of you for the help.


P.S.: If a guy in future finds the calculation formula for the vias in respect of current and resistance.. please post it.

[2X]

Also, I made one more revision with more vias for better heat dissipation of the mosfet.

[Kean]

Also, I made one more revision with more vias for better heat dissipation of the mosfet.

Seems a bit excessive unless mounted on a heatsink.  Hopefully all your solder paste won't be wicking away into those vias.

[2X]

When I go to Fabrication Outputs Final the vias are not visible on the pad where I placed them.
How can I make them visible?

P.S. The same happens on the thermal pads from DFN footprints... the vias don't display on the Fabrication Outputs.

[Doctorandus_P]

Also, I made one more revision with more vias for better heat dissipation of the mosfet.

Seems a bit excessive unless mounted on a heatsink.  Hopefully all your solder paste won't be wicking away into those vias.

Indeed. Looks like a lot of hassle to get this PCB manufactured.

When I go to Fabrication Outputs Final the vias are not visible on the pad where I placed them.
How can I make them visible?

This is normal and expected. For the production output, the via's are never visible on a copper layer. There is no etching for the via's, but the holes are just drilled through the copper. So the only way to verify is to combine the artwork (Gerber) files with the drill files and load them in a gerber viewer.