16 Layer Board PCB 1 GHZ clock

[Mitz]

What are the PCB Design consideration while designing a board with a signal layer of 1 ghz clock with 16 layers  PCB. Can anybody help with a case study? I need a design with  1 ghz clock . Like routing from processor to a DDR3.? I am an OrCAD trainer so I will use PCB designer and ORCAS SI .

[TiN]

Intra-pair length matching, correct impedance (which depends on design topology and used memory controller), solid reference planes.
Basically you want to minimize signal integrity issues as much as possible, while still maintaining design specs.

Also in memory buses it's also important to match data and control signals in relation to each other, so your data will arrive in correct setup/hold windows.

For particular examples you can take a look of DDR3 implementations using Altera or Xilinx FPGA's.

[free_electron]

Layer stack is important. Where you put the power and return planes, the prepreg thickness.
That is going to drive the width and clearance you can attain to maintain impedance.

Next up is length equalisation.

And keep track of the return currents. At 1Ghz you are strongly coupled. So any moat in the return is a disaster (watch out for plane starvation due to via and pad thermal spokes)

[nctnico]

16 layers is a lot! My SoC designs usualy have 6 layers. You can reduce the number of layers significantly by using a power plane as a reference plane for high speed signals. The only caveat is that you need to place capacitors between the planes where (and if) a high speed signal changes from one reference plane to another so the return currents have a proper path. With some optimisations it usually is possible to keep all DDR3 data and clock traces on the top layer.

[Mitz]

Thank you guys.