For DDRx it's typically done as a "clamshell" design, when ICs belonging to different ranks are directly opposite - rank 0 is on the top side, rank 1 is on the bottom side, using the same vias. Memory controller need to support this feature (because DDRx IC balls are not mirror-symmetric), and many of them do, but not all. Take a look at any DDR3/4/5 dual rank DIMM/SO-DIMM, and you will see what it looks like in the real life. This way stubs are minimized (especially if via-in-a-pad tech used), so there is only a relatively minor signal degradation, though for some controller it can be enough to force lowering operating frequency.