SDR Sdram Layout question

[filssavi]

I want to use external SDR SDRAM (alliance memory AS4C8M16SA 128 Mbits, single IC) for my next project with an STM32F429 MCU, I'm now at the layout phase, I have done a first layout (mockup, it is not complete), I'm trying to get a reasonable length matching(still working on that and by what I can seam to find online this is not iper critical), and the tracks are on the short side 74 mm in at max, but mostly under 55 mm, what  my question is do I really have to keep 50 ohm impedance or can I get away without it

Now I did the following calculation:
On the datasheet  of the mcu i find the worst case/smallest rise time (very high speed, CL=10pF Vdd>2.7) which is 2 ns, to get to the bandwidth i use the following relationship BW[GHz] = 0.35/tr[ns]  this gives me a maximum frequency of 140 MHz.

Now We know that the wavelenght lambda=c/f  that in this case results 2.14 m so my  traces are at least 1/25 of the wavelenght and by what I have been thougt I can consider them short and have them in a unmatched

Am I right? will it work? and more importantly will it have any chance of passing EMI tesing (EU if that matters)

[nctnico]

The best thing to do is use a board with at least 4 layers. By optimising the data lanes you may be able to route all data lines on the same layer. You'll need to pay carefull attention to the address and clock lines as well. The drawback of using SDRAM is that the address, control and data lines run at the same frequency and you will likely have to match the length of all these traces but this is something you'll have to look up in an application note of the microcontroller and the memory. I strongly suggest to use the memory noted in the microcontroller's datasheet/appnotes!

BTW: It may sound weird but using DDR memory is much easier because each byte lane has it's own clock and the address/control lines (practically) run at half the clock rate.

[Yansi]

Oh, the classic. "match the lengths". I always ask why, but never got any useful answer. I think it is not required at all, at these clock speeds. And with the STM32 chips, you are very not likely to route it on a single layer. The pinout of the SDRAM controller is very ugly scattered accross the package.

If the clock period will be 10ns or slightly more (as the STM32F429 will likely run the SDRAM at 84 or 90MHz), it should really not matter, if one line is an inch or two longer or shorter than the other, because the propagation velocity will be something like 150ps per inch. The SDRAM won't likely give a fuck, if one signal will be like few tenths of ns sooner or later, than the other. The timing difference that will happen there due to length missmatch (if keeping the missmatch somewhat sensible) is likely insignificant compared to the timining headroom that the controller offers.

I have also confirmed on few of mine and my friend's designs, that the SDRAM @100MHz works absolutely fine on lengthwise missmatched lines. What you should care for more, is the impedance, than the length (to minimize reflections and ringing). I have also experimented with connecting another stuff to the memory controller on the same lines the SDRAM is connected to (to be exact, I have added a NAND FLASH memory chip on the data bus) - so the data lines and few address lines had a big long stubs. It worked without a glitch. A if there was one, I haven't really noticed it. 
My friend even experimnted with only two layer layouts for MCU+SDRAM (that was some Renesas RX something...), where the length matching certainly wasn't possible, nor was possible to achieve the correct impedances. It probably also worked completelyfine. Might have been an EMC disaster, but certainly not a data integrity one.

I may be completely wrong, but I am stating just based on my own experience and the best judgement I have.

And by the way, the ST's original STM32F429I-DISCOVERY kit (uses the MCU the OP mentioned above) to my best knowledge does NOT have line lengths matched for the SDRAM and also all of the lines (data, address and control) have unterminated stubs, that go to the pin headers on the side of the kit. And the kit surprisingly works, absolutely fine. 

[filssavi]

Yes I Can confirm the pinout is quite atrocius the adess and data lines are scattered around the package in random nibbles or even pairs at time, so I need quote a few vias tuo route them there is nothing that can be realistica l'altro done about that, I am already  at 4 layer so I probably can get the inpedance in the ballpark of 50 ohms

[vzoole]

As you (not)see in any SDRAM datasheet, there is nothing about length matching and impedance control.
So you don't need it, but keep the layout as clean as possible.
You need proper reference plane and EMC will be fine.

[ovnr]

As you (not)see in any SDRAM datasheet, there is nothing about length matching and impedance control.
So you don't need it, but keep the layout as clean as possible.

Need, perhaps not. You should still try to get the lengths similar, if not matched. Extreme outliers should be avoided.

[nctnico]

Oh, the classic. "match the lengths". I always ask why, but never got any useful answer. I think it is not required at all, at these clock speeds. And with the STM32 chips, you are very not likely to route it on a single layer. The pinout of the SDRAM controller is very ugly scattered accross the package.

If the clock period will be 10ns or slightly more (as the STM32F429 will likely run the SDRAM at 84 or 90MHz), it should really not matter, if one line is an inch or two longer or shorter than the other, because the propagation velocity will be something like 150ps per inch.

There are a few potential problems though: for example if your clock line is short and the other lines are long then the clock may arrive too early. If you add up all the timing margins and uncertainties you'll find that there is a very small window (several ns if you are lucky) in which the signals should arrive at the chip related to the clock edge. Also: a piece of trace has quite some capacitance (around 0.4pf per cm for a 0.2mm wide trace)) so depending on the drive strength of the chips this may result in considerable delays between the signals if they have very different lengths.

[Yansi]

If the timing margin  window is so low that tenths of ns do matter in the layout, I'd say there is something wrong with the memory controller design.  I admit I have not investigated what the timing margins with these MCUs are by the datasheet, but would really be a problem if it would not tolerate a single ns of delay. If the margin can tolerate at least 1ns additional prop delay (which I think it absolutely does), you still have about 1ns / 150ps per in = 6.7 inches of transmission line (170mm for those who can't imagine). And if you cannot fit your design with lines shorter than 170mm, then, I'd say there something wrong with ur layout then 

I think there really is absolutely enough margin, for any usual MCU - SDRAM layout configuration. More likely you will get caught with impedance mismatch, ringing and EMI problems, than compromising the data integrity in a 100MHz synchronous single-edge clocked design by having not matched the lengths.

Also, good point there to keep an eye on the clock line, so isn't significantly shorter, than the others.

[filssavi]

Ok in what I consider my final layout I have all 50 ohm impedance traces following the pcb house stackup (calculated with Saturn PCB calculator), and unbroken ground/supply plane below them

Lenght matching wise I have, a 6 mm maximum lenght unbalance between control signals, 27mm between adress lines, and 43mm between data lines 1and the clock signal is not particularily short/long


looking at the MCU datasheet i have between 1 and 3.5 ns of valid time for most of the signals which should  quite easily fit in my margins

Thanks to everyone that helped me 

[Yansi]

How do you get 50ohm traces? That seems impossible on the usual stackup. Usual 4 layer PCB manufacturer I use uses 0.2mm prepreg. 50ohm would require something like a 15mil trace on the commonly used FR4 board. You are not gonna use 15mil traces or special thin prepregs, are you?

I think the usual impedance for these applications used is higher, than 50ohms. Terminating resistor can be also used to match the line impedance to the chip I/Os. However I admit I never got any grasp on this and use simply an 8mil trace on 8mil prepreg PCB, which is something like 65ohm impedance at 100MHz "FR4" Er4.6

Also interested to note I have not seen any impedance values for the I/Os in the datasheets of the chips I have used. Neither the STM32 datasheet specify the I/O impedance to my best knowledge.

[filssavi]

right now i used 12 mil (0.33 mm actually) traces on 0.2 mm prepreg that get's me to 50 ohm, the capacitance shouldn't be too big of an issue since it is always under 10 pf (calculated by saturn pcb, value at which the MCU datasheet specifies timings), admittedly the spacing between traces is quite small in some areas, so i hope crosstalk won't be too much of an issue

I know about series termitators but i'd like not to use them since the design is already quite packed as is 

As for the 50 ohm I found it in the micron's TN-46-14 app note where they recomend 50-60 ohm impedance, but they go on to recomend 60+-10% i could just reduce the track's width to accomplish that

[Yansi]

Yes, crosstalk will be an issue an the impedance sure won't be 53ohms for the traces close together. Thats why I talked about impossible 50ohms.  You would need unusably wide traces with wide spaces between them. Use the Saturn toolkit again to calculate that.  The design simply is not gonna happen at 50ohms, not easily.

[filssavi]

 :-+just tweaked the layout to get 8mil tracks and 12 mil spacing 60(ish) ohm impedance hope it's enough

[nctnico]

Impedance matching for memory only gets critical with very long traces (multiple chips or modules) and extremely high speeds (hundreds of MHz).