Should I learn VHDL-AMS?

[suspension]

I have a book printed in 2003 called The system designers guide to VHDL-AMS which I never had time to read. Today I just browsed through the TOC and it looks pretty interesting. It uses VHDL-AMS to model a complete RC airplane as a case study. The whole system including communication, control, electronics, etc. is modeled using VHDL-AMS.

I am wondering if I should put some effort into learning this language with a goal of maybe using it in my pro-hobby projects and possibly to see if I can write a simulator supporting it. (I am an experienced software architect/engineer). I am already familiar with Verilog for digital modeling and C++/Java for software. Also, it is nice to understand how VHDL-AMS compares to Modelica and Verilog-AMS.

[SiliconWizard]

It's interesting, but I have personally yet to see it used in any real, non-academic project. I also personally don't know of any easily available tool supporting it.

Indeed, your best bet these days would be to use Modelica instead IMHO: https://modelica.org/

Now if anyone has any specific experience with VHDL-AMS they can share, along with actual tools - ideally free or at least affordable - I'll be all ears!

[jmarkwolf]

When I got out of school 33 years ago, another engineer warned me I better learn VHDL or I'll be a dinosaur in short order.

I never learned it. I've never missed it. Never met anyone else who uses it. Who needs another layer of abstraction?

[dobsonr741]

The -AMS would give continuous time analog sim. If you fine with Verilog, and it’s not your work mandated tool I do not see a reason why would you do a niche VHDL-AMS and not to choose Spice if you want analog simulation. Most people on this forum can advice you on Spice, but I bet zero on AMS.

[georgfour]

I have faced recently with this language. Maybe we work in the same company? I also have this book.
Honestly, there is no reason to learn it. There is no free tool to compile it, and much more promising is Verilog AMS, it supported by all commercial tool and recently open source Verilog-A compiler appeared (Open VAF). Even Verilog AMS is rarely used, and I have never seen people used VHDL AMS. I have access to xpedition AMS, and I am not impress by it.
Modelica has open source realization and a lot of examples, if you want to try system level multi disciplinary modeling.