SOIC 8 150mil and 208mil in one Footprint

[mattselectronics]

Hello,

For one of my projects, I want to use a flash memory IC from Winbond (W25Q16JV). This chip is available in multiple packages.
The options with the best availability are SOIC8 150mil and SOIC8 208mil.
Because of the current situation with low availability of semiconductors, I would prefer to have the option to use both SOIC 8 package options.

The difference between 150mil and 208mil is, that the 208mil package is about 1.9mm wider.
I would assume, a footprint with longer pads should serve both packages.
I am a bit concerned, that if using the wider package, there would be solder paste under the package causing issues.

Does anybody have experience with this kind of multi package footprint?
Are there any better options to accommodate both packages?

[T3sl4co1l]

I don't think it's a problem.. the flux likely gums up underneath, and is a pain to clean.  If it's washable, maybe avoid vias underneath so there's less exposed metal to corrode.  Errant solder balls stuck to the PCB or package, don't really matter, and most will coalesce into the pad.  Somewhat less paste might be used, given the excess pad length, but it also still needs to span most of the length of the pad else there won't be enough flux and spreading ability to tin the whole thing for both components (i.e. don't make a pile at just the heel or toe).  So, probably a bit of negative paste expansion would be the most you'd bother with.

Note that heel can be set to minimum or even somewhat negative, for the narrow body part -- most assemblers are only interested in one fillet, which would be toe in this case, and the heel then is optional.  Note a severely negative heel will emit a "pin on soldermask" error from most DFM tools, which you may or may not wish to honor.

I think pin-on-mask probably doesn't matter too much here, as the radius of the solder blob (meniscus) on the pad should be pretty generous for SOIC, thus even a fairly tilted component should still dip into the blob and make a connection.  (Or if the pin melts first, then that blob onto the pad, whatever.)  I'd be more worried about that for fine pitch (TSSOP etc.?) where the pad width is much less, I think?

I don't think I'd go so far as to halve the joint face area (effectively dimension L, but in the solder joint, from pin tip to pad heel), but you can still see where it takes you with minimal heel or a little under, with respect to body sizes, and tolerances.

Tim

[mariush]

You could have the small 150mil SOIC footprint rotated 90 degrees and squeezed within the footprint of the 208 mil SOIC  - you'd just have a few vias to add to make the connections.

I would also consider adding WSON - with a bit of tweaking of the pads you could make it sit in the same footprint as 208mil soic  - see the mockup picture I made in paint to see the relative dimensions


EDIT:  Macronix has an application note with a footprint mixing 209mil 8SOP with WSON  : https://www.macronix.com/Lists/ApplicationNote/Attachments/1886/AN182V1-209mil%208-SOP%20and%206x5mm%208-WSON%20Dual%20Layout%20Guide.pdf

unless I'm mistaken ... SOP and SOIC is same dimensions so maybe check it out.

[T3sl4co1l]

Is that SON, or DFN (no middle pad)?  The former might be a little awkward, though I think it's just small enough to fit all three (or four even) in the same place.

Tim

[Benta]

No problem at all, I've seen this done dozens of times, mostly with SO-16 and SO-16W. Normal practice.

[mattselectronics]

Thank you for all the comments.
I made the footprint in the attachment.
The inner distance between the pads is a bit wider than normal for the 150mil package (4mm).
The outer distance is 8.8mm, so it should be wide enough for the 200mil package.
The 200mil package body is 5.2mm wide, so it will only overlap the pads by 0.6mm each side.
I hope there won't be any issues with this design.

[tooki]

unless I'm mistaken ... SOP and SOIC is same dimensions so maybe check it out.

You are mistaken, they aren’t the same. (Same pin pitch, different package widths.) With that said, semiconductor manufacturers and vendors are extremely sloppy about the terminology and often mix up SO and SOIC, using the wrong name. So in the end, it’s essential to verify the actual drawings.

[wraper]

You could place pads from one side of one footprint into another footprint. It will take a bit more space than a single footprint however no soldering problems will be guaranteed.

[PlainName]

That kind of limits the routing. But if you placed the 5-8 pads (or 1-4 pads) on top of each other then a short track to link the other side pad pairs, and routing is the same as for the narrower part. Plus board space is the same as for the wider part.

[mattselectronics]

You could place pads from one side of one footprint into another footprint. It will take a bit more space than a single footprint however no soldering problems will be guaranteed.

I would guess, that you need a stencil for each variant. Generation of the gerbers for this stencils is probably also quite a pain.
Routing is probably also not as easy.

[wraper]

You could place pads from one side of one footprint into another footprint. It will take a bit more space than a single footprint however no soldering problems will be guaranteed.

I would guess, that you need a stencil for each variant. Generation of the gerbers for this stencils is probably also quite a pain.
Routing is probably also not as easy.

Solder paste under SOIC package poses to issue as it has significant gap under it. If you are concerned about washing flux residues under it, it's much harder to do under MLCC, resistors, and other components that lie on PCB without a gap.