Stuck in PCB routing: where do I go from here?

[exscape]

Here's where I'm at:

As the finely-drawn arrows indicate, I need to route those pins across the thick 5 V trace that goes through the middle of the microcontroller (the DIP package, U4).
What's the best technique for doing so?
This is on a 2-layer board, where the bottom layer will be a ground plane. Some of the pins are relatively high frequency, 8 MHz SPI. I can lower that frequency if needed, but I prefer to do this properly, over doing it badly and slowing the circuit down until it works.

Routing around isn't an option, as the power trace goes pretty much from top to bottom of the PCB.
My first thought was to use vias for the signal traces, but that'd make 12 of them (if I bring them back to the top layer again)...
My second thought was to move the 5 V trace (the Y-split part) onto the bottom layer, but then I'd be routing the signal traces over a split in the ground plane. Not good for signal integrity/EMI.

This is my first proper PCB layout, by the way, so I'm indeed new to this.

[8086]

You can drop the 5V trace down and then back up for a short run, shouldn't cause problems.

[jeremy]

is there a reason you can't shift the isp to the left hand side and move your reg over ? anyway, unless your design critically depends on a ground plane with exact geometry (at 8Mhz, I assume not), I don't see why dropping a few power tracks down for a little bit should be a problem. Some of the guys I work with would consider 8Mhz to be DC!

Perhaps it would help to know what you are building. Good luck!

[HackedFridgeMagnet]

Can you do a surface mount zero ohm link for the 5v and run the tracks between the link? Obviously it would need to be fairly large the gap, or you could do multiple links like this.

I think I would just use the second layer for a short bit of 5v. As the ground plane is already broken by the through hole stuff anyway.

ps. I am no expert at this.

[mikeselectricstuff]

Small breaks in a ground plane are not a problem in the vast majority of cases.
The general technique for mostly SMD boards is to do as much as you can on the top layer, and do small jumps via a the bottom layer ground plane where necessary, and when finished space them out or group them together as required to avoid splitting the plane
PCB layout will always be a compromise, and all rules and recocmmendations are flexible.
Things which are critical on PCBs using things like 24 bit ADC or  1GHz+ radios can be completely ignored on most run-of-the-mill PCBs. Also remember that you generally have routing space around the edge on both sideswithout worrying about cutting things off.
The only absolute rule is that good placement is everything!

[exscape]

is there a reason you can't shift the isp to the left hand side and move your reg over ? anyway, unless your design critically depends on a ground plane with exact geometry (at 8Mhz, I assume not), I don't see why dropping a few power tracks down for a little bit should be a problem. Some of the guys I work with would consider 8Mhz to be DC!

Perhaps it would help to know what you are building. Good luck!

Heh, I know that 8 MHz is pretty much "spare change" to the pros, but I still prefer to "do it right", as one of the main project goals is to learn!
I could probably have the ISP over there, but that's only one of three things that needs SPI.

The board is for a data logger (or perhaps rather data acquisition) - AVR microcontroller, SPI Ethernet module, temperature sensors and a socket for a future daughter board (with I2C, SPI, a few other AVR pins and power routed to it). My placement is probably not ideal from a routing standpoint, but I doubt I could place it such that all these issues go away - but I could probably reduce them.

The general technique for mostly SMD boards is to do as much as you can on the top layer, and do small jumps via a the bottom layer ground plane where necessary, and when finished space them out or group them together as required to avoid splitting the plane

In other words, make many smaller "cuts" into the plane, and avoid making longer ones?
How small is "small", though? I do realize that this board will work either way (it works on breadboard with jumper wire, at 8 MHz, and I assume even "bad" PCB layout is superior to that).

Also remember that you generally have routing space around the edge on both sideswithout worrying about cutting things off.

Hmm, not sure what you mean by that.

Anyway, here's a quick and ugly test:

Would something like that be fine? Or, rather, up to what frequency / edge rate would it be fine?
The end result will of course be neater and all.

In either case, thanks for the answers so far!

[mikeselectricstuff]

Heh, I know that 8 MHz is pretty much "spare change" to the pros, but I still prefer to "do it right", as one of the main project goals is to learn!
I could probably have the ISP over there, but that's only one of three things that needs SPI.

Doing it right means knowing which things are important for a particular design. There is almost never a right or wrong way, just more or less appropriate in a given situation.
For an 8MHz AVR, as long as the crystal leads are short you would have extreme difficulty making a layout that would not work just fine, even if it looked a mess.

The general technique for mostly SMD boards is to do as much as you can on the top layer, and do small jumps via a the bottom layer ground plane where necessary, and when finished space them out or group them together as required to avoid splitting the plane

In other words, make many smaller "cuts" into the plane, and avoid making longer ones?

Yes.  It's not so much the effect of the size of the cut as the fact that bigger cuts eventually join up and break the plane completely. So only go there for as long as needed, and also when you've finished, take a fresh look to see if anything can be moved back off that layer, or the length on that layer shortened.
Once you have nearly finished, you will have a bunch of random bottom layer links that make holes in the plane, or maybe even break it apart. You can usually move these around to make sure you have enough plane between them to make it all join up, and sometimes the trick is to move two parallel ones closer to each other so you get 1 slot in the plane instead of two. For example with 10mil line/space design rules, one trace will cut 10(space)+10(track)+10(space)=30mil out of the plane, but two parallel ones will only cut 50mil.
It is generally hard to visualise the effect of a bunch of links until you re-pour the copper fill, at which point it will often be obvious which links could be moved to improve things

How small is "small", though? I do realize that this board will work either way (it works on breadboard with jumper wire, at 8 MHz, and I assume even "bad" PCB layout is superior to that).

No bigger than you need to get where you are going, often even if it means 2 small jumps instead of one long one.

Also remember that you generally have routing space around the edge on both sideswithout worrying about cutting things off.

Hmm, not sure what you mean by that.

I mean don't regard the whole bottom layer as "sacred". You can run noncritical tracks around the edge without issues, and also run long tracks around the perimiter on the top layer without cutting anything off. But best to leave these to later in the layout.

For most run-of-the-mill designs, minimising use of the bottom layer for routing is more about preserving potential routing space for when things get tight than any electrical considerations.

See the attatched GIF for an example of a dense 2-layer layout - this is a 2-layer PCB with a 144 pin FPGA, TSOP flash and a couple of 45 way FFC connectors.
At top left and bottom, long tracks at the edges which would have taken a lot of routing space on top.
At the bottom centre. vertical tracks tightly grouped to minimise the cutout area, but enough gap left at the bottom to the horizontals below to maintain the plane around them.
The plane is actually cut off at bottom left, but strapped across by a wide track and multiple vias on the top layer - there isn't anything critical connected to that part of the plane so the inductance of the straps & vias isn't an issue.
Line cuts in the plane at the left to contain the circulating noise current in a DC-DC converter.
Multiple short wide horizontal straps in the centre to join up a topside power plane under the FPGA which was split by a second power rail. Multiple wide joins minimise inductance of the jpin while keeping a decent width of groundplane

[exscape]

How's this?

I'm not overly happy, nor am I done yet (*most* things are routed, but still not finalized/cleaned up), but I figured some quick feedback now is more valuable than later on.
There are a few things I wonder about:

1) The AVR reset line, pin 5 on the ISP, runs relatively far on the bottom layer. Is this better than adding 2 more vias under the micro, near the crossing traces?
2) Is it bad to group the traces like I've done (the ones going down bottom right, and the ones below C9), regarding crosstalk, noise etc.? When does crosstalk generally matter? The ones under C9 are SPI traces (nominally 8 MHz).
3) In general, how much do vias add to noise / how much do they affect signals ("high" frequency, but say below 10 MHz)?

Of course, general feedback is also welcome.

[8086]

The reset trace can have as many vias as you want really, it's not exactly high frequency

I would personally route that trace with more vias and find a way to get rid of the vias on the TX and RX on the right.

Route the higher speed signals first, then make the rest work around them. That's my usual approach.

[exscape]

The reset trace can have as many vias as you want really, it's not exactly high frequency

I would personally route that trace with more vias and find a way to get rid of the vias on the TX and RX on the right.

Route the higher speed signals first, then make the rest work around them. That's my usual approach.

Oops, the RX/TX deal wasn't very thought through. It's not as if the LEDs need more signal integrity than the UART.
I'll swap those, at least, or route around.

Regarding the reset trace, I'm mostly concerned about noise. I'm likely taking an overly cautionary approach when it comes to things I'm unsure of, so my current thinking is basically that vias = death for everything.

[mikeselectricstuff]

The reset trace can have as many vias as you want really, it's not exactly high frequency

I would personally route that trace with more vias and find a way to get rid of the vias on the TX and RX on the right.

Route the higher speed signals first, then make the rest work around them. That's my usual approach.

Oops, the RX/TX deal wasn't very thought through. It's not as if the LEDs need more signal integrity than the UART.
I'll swap those, at least, or route around.

Regarding the reset trace, I'm mostly concerned about noise. I'm likely taking an overly cautionary approach when it comes to things I'm unsure of, so my current thinking is basically that vias = death for everything.

If your reset is susceptible to noise pickup on a PCB trace then the pullup is too high.