Thermal Via Layout Help

[scott216]

I have a PCB I'm designing (home project - nothing industrial) where I have a TLE4476 voltage regulator (Digikey TLE4476DCT-ND).  It comes in a TO-252-h package.  I'd like to add some thermal vias to conduct heat to a copper rectangle I have on the bottom of the PCB.  I want to know if there are some guidelines regarding thermal via size and spacing.  I'm using Eagle.  Also, is there anything special I need to do other then just adding a bunch of vias.   I'll probably have OSH Park make the board.  I will be using my DIY reflow oven to populate the PCB.

[T3sl4co1l]

Search for appnotes on the subject; there's a lot of info out there, especially regarding power packages (exposed pad types and etc.).

You can do via-in-pad, but the vias slurp up solder, which is a bad idea for manufacturing with paste and reflow.  I suppose you'll be hand soldering these anyway, so just add solder until there's a neat fillet around everything; if it's oozing out through the vias, it's probably a good thing (more metal!).

You can place vias around the perimeter of the footprint, so there is no exposed soldermask connecting them to the pad.  This puts more copper between heat source and sink though.  You can't expect much out of an SMD part anyway, so the ring-of-vias method is pretty good.

Use vias you are comfortable with, big enough and numerous enough to do the job.  I would say, use no less than the amount of copper connecting to the pad:

Suppose the pad is square, 10 mm on a side.  That's 40mm perimeter.  Suppose the board is 35um stock, plated to 70um (2 oz. finished foil thickness), with 35um via wall thickness.  That 40mm perimeter is in 2oz. but the vias are 1, so you need 80mm worth of via perimeter to equal that.  A 0.5 mm via has 1.57 mm circumference, so you'd need on the order of 50 vias to equal that.

You can make whatever excuses you like: the backside copper pour will only dissipate half the power (ideally speaking), so it doesn't need the same cross section as the footprint itself.  So 25 vias.  Maybe you don't need as low a thermal resistance -- PCB heatsinking sucks anyway, and a 50 mm square region isn't going to handle more than a few watts before it's too hot to deal with.  You won't loose *too* much by skimping on vias here.

Normally, I go with 20 mil vias, spaced 40-60 mil apart, in rows, along three or all four sides of the pad.  For a D2PAK, maybe 6-8 per side, or 18-32 total.

Follow the manufacturer's requirements on design rules, spacing, etc.  Usually you can't put holes closer than 10 mil, edge to edge; EDA tools usually flag putting a hole through another component's copper, or overlapping shapes, so that a 20 mil via can't be spaced closer than 30-60 mil depending on annular ring (if specified, or if derived from design rules).  Assuming you obey the DFM checks that is.

Tim

[AlfBaz]

Curiously I have an android app on my phone that can calculate thermal resistivity of a bunch of vias from one plane to the next. You can buy just the thermal module here https://play.google.com/store/apps/details?id=mwave.thermal_pcb

The help file stipulates that the bottom plane has to be the same size or larger than the top for the calc to be accurate

Unfortunately you have to move the heat away from the bottom plane as well otherwise after a while you'll reach equilibrium and be in the same boat as you were without the sink.

[scott216]

You can place vias around the perimeter of the footprint, so there is no exposed soldermask connecting them to the pad.  This puts more copper between heat source and sink though.  You can't expect much out of an SMD part anyway, so the ring-of-vias method is pretty good.

Thanks Tim.  Can you elaborate on what you mean about "no exposed soldermask"?  I'm not following this.

BTW - I could probably get away without any thermal vias.  I'm working on rev 2 of this board now, rev 1 didn't have any thermal vias and the LDO was pretty warm, but not really too hot.  I thought since I'm doing an new PCB version, why not give thermal vias a try.

[T3sl4co1l]

Solder mask, as in, the shiny metal ring around the vias doesn't touch and merge with the pad area.  So solder could wick along said metal, and get sucked into holes...etc.

Vias can also be tented, even plugged: which is sometimes done within a footprint, if it's desirable to prevent solder wicking into a via-in-pad design.  This, I think, is more of a concern with exposed pads and QFNs, where a precise amount of solder is required to ensure a solid connection without voids, while avoiding an excess from pushing it up off the surrounding pads.

Tim