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To Flood or Not to Flood Multi-Layer PCB Internal Signal Layers

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I do realize this is similar to the following post:

However that post was targeted more for simple 2-layer PCBs.  My question is I'm looking for industry expertise on the following question.

If you have a multi-layer PCB with X number of internal signal layers, upon routing completion of those layers and into DFM review:

Do you Flood or Not Flood the "open" areas of these internal signal layers with copper?

Assume designs of 8-layers and above...  (10 to 14 being typical for our designs)

The answer is "it depends". Signal layers' ground fills need to stay away from impedance controlled traces as nearby ground will change their impedance. Other than that it can be a good idea as fill factor can affect final prepreg thickness - again this is important for impedance controlled boards. But normally PCB fab will handle it as impedance difference is usually less than typical 10% tolerance for CI. But this will be important if you have very high-speed traces (multi-gigabit ones) as you will need tighter impedance tolerance.

It's not entirely clear why there would be any significant 'open' areas in a multi-layer board like that. What's the driving factor behind the layer count? Is there one particular BGA that needs all those layers to escape it properly?

I don't personally flood tracking layers without a very good reason. You end up with a lot of little disconnected shapes which end up getting removed anyway, and it's not at all clear that the bits left serve a useful purpose.

If there's a lot of empty space on certain layers, your PCB manufacturer may want to add thieving to ensure uniform plating. If that's the case, for the sake of consistency between suppliers, I always prefer to make the changes in the original artwork rather than ever letting a manufacturer make their own changes.

If it's a controlled impedance board, tell the manufacturer the target impedance, and let them make adjustments to the stack-up and trace width to achieve that impedance. This means you don't have to worry about slight changes in board thickness and layer spacing; the impedance is achieved 'closed-loop' with the manufacturer being responsible for the end result you want to achieve.

No.  Except for very special cases, no.

In ordinary cases, myriad islands and stubs will be formed, which will resonate at random frequencies.  While these frequencies may be in the low GHz, it's still a bunch of stuff that is not needed.  And, as mentioned, it affects the characteristic impedance, when you do need that in a critical design.

If it should be needed, the burden is adding enough vias -- through as many layers as are being paired up for it, if not a plain thru-via process -- to nail down the ends and spans of those islands and stubs.  It takes a lot of work, adding stitching vias -- even if there are functions to facilitate it in some tools, it's still more geometry that you are responsible to inspect, and place and move as needed.

On a 4 or 6 layer board, you're more likely to have thru-vias, which makes a terrible burden as far as trying to place  stitching vias between components and traces on all layers.

I suppose you're more likely to have multiple drill pairs on 8+ layers, in which case you can make some simplifications at least, but you also have that many more layers to deal with...



--- Quote from: gfoundry on November 22, 2018, 07:26:59 pm ---Do you Flood or Not Flood the "open" areas of these internal signal layers with copper?

--- End quote ---


1. Layer stackup must be symmetric. This includes the average copper density. If one layer has very litte copper but the mirror layer is a full plane this might cause manufacturing problems.
2. Even copper distribution: I'm unsure if there might be a problem if one half of a board has a very high copper density and the other half has a very low one.

In doubt ask your PCB manufacturer.


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