TO252 thermal vias

[luky315]

I have a TO252 LDO which gets a bit warm and needs aditional cooling (layout attached). When the Tab is GND I would place a lot of thermal vias to spread out the heat into the ground plane(s). But this LDO has Vout (3.3V) on the Tab and most of the VCC-Plane is reserved for another (more critical) supply voltage. I can't connect the heat source directly to a big copper area.
Are there any design considerations for this kind of problem?

[tszaboo]

First thing you should do is: put a fill or solid region to overwrite the poligonconnect design rule. Then, if you can, make a poligon on the other side of the PCB, and connect it to the vias. Also, make sure, the vias are not connected with relief. Remove solder mask on if possible, but of course keep some around the footprint. Extend the copper on top as mucha s possible. You might want to increase the density of the vias. Also, I'm not sure about the diameter you are using, but AFAIK 0.3mm-0.4mm is the best. Somewhere I read that more than two rows of via has very small effect.
If nothing helps, there are SMD heatsinks, which you can solder "around" the component. If you bring the ground plane close (~0.2mm)to the VCC that also helps. How much are you dissipating? How big is the pour you have?

[luky315]

There is a connected Polygon on the Bottom layer. The Via diameter is 0.5mm and there are no thermals on them (I don't know a good reason for thermal reliefs on vias. No Idea why it's the Altium default setting...) I need the thermal relief otherwise the production guys will kill me. Of course it would be great not to use thermal reliefs and to put thermal vias directly under the component, but than you can't solder it with a normal reflow process.

[lorth]

(I don't know a good reason for thermal reliefs on vias. No Idea why it's the Altium default setting...)

It helps when soldering components to large cooper planes/traces, you need less heat (and less time with the soldering tip on the pad). Also, it avoids tombstoning when mass producing.

[luky315]

I use the thermal reliefs on the pad (and a symmetrical connection) to avoid tombstoning. Thermal reliefs on "Ground"-Vias add unwanted inductance.

[tszaboo]

There is a connected Polygon on the Bottom layer. The Via diameter is 0.5mm and there are no thermals on them (I don't know a good reason for thermal reliefs on vias. No Idea why it's the Altium default setting...) I need the thermal relief otherwise the production guys will kill me. Of course it would be great not to use thermal reliefs and to put thermal vias directly under the component, but than you can't solder it with a normal reflow process.

Yes, I'm aware the problems which might occur if thermal reliefs are not used. But that is something you dont want to do if you use a power device. The reason for thermal relief is to avoid tombstoning. A TO 252 component will not tombstone. Nor will they have any problems if they use sufficient preheat. the worst case scenario is that the component will drift a bit, but as long as it is within the pre-defined region, i dont see the problem with that.
But it worsens the situation after production. FR4 conducts heat some 2000 times less (if I remember correctly), and that is not something you want there.
If production guys complain, tell them that then you need to use a TO220 with heatsink, screw mount it with isolation, they will scream and run away or agree with you.

[luky315]

So you would suggest removing the thermal reliefs from the Tab and maybe placing thermal vias directly under the Pad? I can't plug the Vias (cost reasons...) and the minimal via diameter for this Project is .35mm, which in my experience is to big to prevent the solder from flowing through. And I don't trust soldermask covered Vias.

[tszaboo]

So you would suggest removing the thermal reliefs from the Tab and maybe placing thermal vias directly under the Pad? I can't plug the Vias (cost reasons...) and the minimal via diameter for this Project is .35mm, which in my experience is to big to prevent the solder from flowing through. And I don't trust soldermask covered Vias.

Yes, I would remove the thermal relief for the pad. I usually do in my designs.
TI has a big application report for QFN packages http://www.ti.com/lit/an/scba017d/scba017d.pdf (hey link button, are you broken?) also, http://www.ti.com/lit/an/sloa122/sloa122.pdf I know that QFN is not TO, but close enough.
There they use 0.3mm vias, they wrote somewhere that above that via wicking might happen. 0.35 is probably fine. I also wouldnt put solder mask covered vias under a package.  maybe you can get away if you put bigger solder paste mask openings there.
But do you know the expected dissipation?

[luky315]

The regulator works with the current layout, but only at room temperature. In the thermal chamber it goes into thermal shutdown. The current consumption is irregular with high peaks (up to 1A) an long sleep periods.
 I made a new layout with .25mm Vias. I hope this works.
It's my first "low cost" design. Until now I worked on projects where the cost of the PCB was negligible and we could use expensive technologies (plugged vias, vapor phase soldering...)

[Niklas]

One way to control which pads and vias that are connected to the copper polygon using thermal relief is:
- Convert vias to free pads by selecting the vias and apply (Tool, Convert vias to free pads)
- Rename the vias with the PCB inspector down in the right corner. Default in 0, but maybe something else is more suitable?
- Create a pad class and add all the pads you would like to be non thermal relief ones. (Design, Class, New pad class, add all pads you like)
- Add a new polygon connect style rule to the design rules. Advanced query with pad class and polygon. Give it high priority.
- Repour polygons and check the results.

[toohec]

Just a quick FYI...

I use these "Therma-Bridge" parts for transferring heat in space-limited regions where the heat slug is not at ground potential.  They basically look like surface mount resistors/capacitors, but provide a thermal path for the heat while maintaining electrical isolation.  For instance with high heat disipation parts, I'll add a therma-bridge as close to the heat slug of the part, and place a mechanical mouting screw on the opposite side of the bridge that can then move the heat to the chassis/heat-sink.  Using a combination of a large polygon region in addition to a therma-bridge should provide great results if space allows.

These are the parts I use in a 1020 package.  There may be other manufacturers as well.
http://www.ims-resistors.com/Thermal_Management.html