What are the names of metal additive processes to make PCBs?

[Merlysys]

I only know of processes where the board comes bearing copper and most of it is removed showing just the traces. How about the opposite way?

Can the metal be deposited when certain areas are targetted say, charged positive or negatively like paper in a laser printer?

How about laser based methods?

There is Cartesian Co's Argentum 3D printer that deposits metal right onto the PCB. Nobody has mentioned it on this site, I wonder if that is due to deposit lines being somewhat crude and not sharp.

[T3sl4co1l]

On a theoretical basis, it's kind of curious that so many additive processes tend to be very generalized (e.g., entire surface, vs. patterned), or one-time only (i.e., PCB stock is made by laminating foil and fiberglass: pre-patterned foil would be ludicrous!).  This is essentially 100% of all semiconductor manufacture: every other step consists of applying a resist, then etching away the excess from the proceeding step (which might be e.g. full-surface deposition of SiO2 insulator, aluminum conductor, etc.).

There are also mechanical reasons.  The average chunk of commercial FR-4 or G10 is glossy, so you wouldn't expect anything to stick very well.  Of course the surface can be sanded, and perhaps other preparations made to prime it for some sort of metallurgical bond.  But perhaps there isn't a process that can achieve as good of a bond as when the core is sandwiched between prepared foils (usually etched and oxidized).

Economy of the whole process is also a consideration.  If you have to draw on traces manually (say, a per-board plotter, or 3D printer type thing), it will take considerable time, which might be okay for prototyping (as long as additional value is had, such as quick turnaround -- and this means, above and beyond what current processes offer today), but certainly won't be adopted for production (which might be where 99% of the market is).

Other examples:
PCB core can be printed with conductive ink, and plated with copper to the desired thickness; but the initial plating process is very slow, because the conductive ink is only just conductive enough to work.  Once a sufficient thickness is down, it can be sped up to normal rates, but the time is already gone.
Or the core material itself could be conductive, and perhaps washed or treated (after the plating is complete) to remove its conductivity.  But likely it will still be very slightly conductive, and fail electrical tests sooner or later.  The additives required to achieve such effect might not age well, leading to degradation.

Tim

[poorchava]

I think microvia PCBs are made with additive process exclusively (the microvia part of the stackup is anyway). I think other name for microvia technology is SBU - sequential build-up).

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[poorchava]

Etching is subtractive, ale but the copper is added from liquid phase or something (definitely not a laminated sheet of copper).

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[free_electron]

metallized holes are typically made as follows ( there are other processes but the one i describe her eis the most common one )

start with a laminate : a core material with two sheets of copper foil. ( top and bottom )
drill holes.
wash and clean ( degrease , desmudge , deburr.)
microetch to remove copper oxidation.
wash
dip in activator : this makes the wall in the drilled hole 'porous' by attacking the resin. on a microscopic level it makes the resin surface rough.
dip in electroless plating solution. a conductive layer is deposited.  in the olden days this was often 'carbon ink', but that process is gone. they deposit copper now.
enter electroplating solution. copper from a donor plate is electrochemically sublimated on the board. this copper grows everywhere : in the hole, on the surface.
in the olden days simple DC current was used. now we employ pulse plating . when plating you locally deplete the chemical in the holes from copper. by using pulses and stirring the liquid you allow a more uniform plating. the exact chemistry i don;t know. i know there is an electrolyisys problem with the water splitting and soemthign with phosporous being deposited as well. by using a long positive pulse to deposiut cooper, followed by a dead time , followed by a short negative pulse to remove a tiny bit of the plating , you create better quality deposit.

once plating is done the board is washed and dried.
dry film photoresist is applied and exposed to the image. the image is NEGATIVE. : the coppe rthat is to remain on the board is bare after developing. the copper to be removed is covered in photoresist.
now the board goes in a chemical tin flash where Tin is deposited on the bare copper ( and thus also in the holes. ) where there is photomask no deposit happens.

the photomask is now removed.

you now have a board where the elements that need to remain are covered in a thin layer of tin. the elements to be removed are bare copper.
the board is no etched in a solution that only eats copper. the Tin acts as etch resist.

once etching complete the tin is chemically removed and you have a double sided through plated board.

[rfeecs]

Thick film circuits use an additive process.  Conductive, resistive and sometimes insulating layers are applied in the form of "ink" by silk screen printing.

https://en.wikipedia.org/wiki/Thick_film_technology

Another sort of additive process is used for creating thick conductors:  deposit a thin blanket layer of metal, deposit photoresist and open up the area where you want conductors, plate up the thick conductors, strip the photoresist and etch everything to remove the blanket metal, leaving the thick conductors.

[codeboy2k]

There is an alternative process to what free electon describes, it's called pattern plating.  Free Electron described what is known as panel plating, where copper is plated everywhere, then a negative dry-resist, then positive tin in the pattern needed, then the copper is etched away. Some shops still do this, but  it is wasteful and more time consuming, because so much copper has to be plated then removed.  More recently, with extremely fine traces, this etching cannot be done anymore as there is too much undercutting of the fine traces during the longer etch time.  So instead of a full panel of copper plating, the dry-resist is put on the thin copper foil that is on the core material, and then only the copper pattern is plated onto the copper foil, to build it up to 0.5 oz or 1 oz, etc. Then tin is plated to protect this copper pattern during the etch, which removes the original copper foil only.  This ensures as short a time as possible in the etchant and no excess copper is wasted.  It's a fully additive process, building up the copper only where it's needed.  The tin is chemically removed at the end, then the final finish is applied like ENiG or IaG or HASL, etc.

Google for PCB pattern plating for more info.

[rs20]

This video covers the whole process, including both additive (outer layers) and subtractive (inner layers) methods. See 14:22 for where the additive processing begins, note that at this stage we have a four layer board where the inner two layers are complete, outer two layers consist of only a very very thin layer of copper, and the holes are completely fresh and have no metal on the walls at all. So stages after 14:22 are adding electroless copper to make the hole walls conductive to enable electroplating, then adding a mask to cause subsequent electroplating to only go where copper is ultimately wanted, and then a final non-masked etch step which removes the very thin copper from the areas masked beforehand. Easier to understand in video form I think!

[IconicPCB]

There are at least a half a dozen methods available to implement hole wall activation.

The now old and tired electro-less copper , carbon black, palladium and red palladium colloidal solutions, plasma/vapor deposition and conductive ink offering.

Each has its peculiarities , weaknesses and strengths. Each can be used in either panel plating or pattern plating process.

Plasma deposition along with palladium are two processes which will tackle Teflon base successfully.

Major advantage of the plasma deposition approach is it calls for bare FR4 base material and it deposits only an atom(s) thick layer of copper , enough to commence plating process. A natural candidate for pattern plating since the etchant has to contend with only a very light copper layer.

There is a technique not used in the west, developed bu Russian technologists during cold war period which relies on copper pyrolysis to deposit a thin layer of copper nano particles.

We are presently using colloidal palladium while investigating the Russian process. Colloidal palladium is an Atotech ( Germany) process but ever since the PCB shops in Australia shut down it is becoming more and more expensive and impossible to get hold of supplies. The supplier NO LONGER carries palladium ( chemicals) and any future supplies while readily available from Germany .. need to be specifically imported and all the surcharges etc need to be met. Expensive and inbuilt into price of our services.

We are also investigating Russian pyrolytic copper method. Had some success but need to learn to control size of deposited nano particles.

[codeboy2k]

I can see the day coming when engineers and systems designers are going to be working more and more with bare dice and the PCB will be so small that it's just metal vapor deposited in a pattern, then the assembly house will just use bare dice from the manufacturers. No one is touching these small parts anymore so we really don't need packages.  NXP has a 1mm x 1mm 0.35 mm pitch no-lead package now, it's barely covering the die.  We just need the assembly house to glue dice down and wire bond them all to tracks like the black blobs in calculators.  That will become the norm.  FR4 will still be used to breakout to the real world connections, but packaging will become obsolete.

[rfeecs]

I can see the day coming when engineers and systems designers are going to be working more and more with bare dice and the PCB will be so small that it's just metal vapor deposited in a pattern, then the assembly house will just use bare dice from the manufacturers. No one is touching these small parts anymore so we really don't need packages.  NXP has a 1mm x 1mm 0.35 mm pitch no-lead package now, it's barely covering the die.  We just need the assembly house to glue dice down and wire bond them all to tracks like the black blobs in calculators.  That will become the norm.  FR4 will still be used to breakout to the real world connections, but packaging will become obsolete.

People have been doing hybrid chip-and-wire assemblies for decades, ever since there were chips.

If anything, the trend is to get rid of the bond wires.  See flip chip, chip scale packages, or wafer level packages.

[codeboy2k]

Yes, I know that it's been done, I even said so. It's just not the norm, and people are still doing mostly PC boards with various parts in SOIC, TSSOP, MSOP, QFN, BGA etc.. I think there's too many packages. We just need hobby level packages for home and everything else can be machine handled, that's what I mean. I just think it will become standard, not just used for specialized applications.     Most packages for machine assembly will go the way of the dodo.

Well, that's my prediction and I'm sticking to it

If anything, the trend is to get rid of the bond wires.  See flip chip, chip scale packages, or wafer level packages.

Yes, and 3D packages too ...

[T3sl4co1l]

I don't think you'll see hybrids take over.  The barrier to entry has always been higher, and there hasn't been any indication that it will fall.  (It would be one thing to have a cheap 3D printed process that includes PnP and die bondout -- this would at least facilitate prototypes -- but quite another to have a pattern-printing process that's actually production-worthy and just as cheap to setup and operate!)

The trend is well underway already: if you're going to go for integration, don't half-ass it, go all the way.  Remember the Pentium Pro, in that rectangular package, that literally had the extra cache strapped in alongside the CPU?  (With the ceramic package, it's kind of on topic.  Of course, multi-die packages have practically always been around, and aren't about to go away.)  More and more CPU-adjacent parts have integrated; today, the "North Bridge" has been absorbed completely so that the CPU includes bus and DRAM control (and maybe PCIe?) functions.

I don't need to say 'soon', because we already have SoCs of supercomputer capability* for just a few watts, peripherals included on chip.  Multicore ARM A9s and stuff at 800MHz+ are astonishing power, for practically peanuts both in money and electricity.  (Not that all of those are fully integrated with every single peripheral, let alone RAM/ROM.  But those are available, usually in the scaled down models.)

*Comparable to, like, an early model Cray or something like that.  80s era, when supercomputing meant one or a few, really freaking beefy and fast, CPUs.

So far, top-of-the-line desktop/workstation CPUs haven't reached that kind of integration yet, but that could have many reasons.  We're talking serious die area, so monolithic yields would be bad.  (Polylithic yields might be bad too, but you're not staked on one chip for all.  That said, they've also been making them configurable after test, to cut out derpy cores or memory segments, which helps recover still more yield.)  Processes aren't necessarily optimal for putting high density RAM (let alone Flash and other) on chip.  Power dissipation is huge and disparate, so it doesn't make sense to put everything side by side, let alone stacked on top of each other.

Which reminds me, I'd like to see full scale development of that "lossless logic" that was talked about some years ago.  There are a few approaches, I think.  The one I had read about was, a system of synchronous, quadrature (or other phased) switches, which connect (or don't) the switching nodes (which have capacitance) to a main commutation rail, which is always transitioning up or down.  Therefore the commutation rail sees a capacitive load (which could be driven by a tuned clock oscillator), and very little gate power is spent forcing capacitances to transition.  The figure given (in the paper I'm thinking of, some logic, a multiplier I think, was fabricated at MOSIS) was ~3x lower density and >10x savings, which seems worthwhile.

Tim