What do you think of my PCB design?

[Christopher]

First library part and "complex" 2 layer board I've done. I know the board looks a bit dodgy, but I plan on sorting out the routing (angles, clearance etc) before production. Also I'll add another segment to the board for a total of 5 .

Basically a 7 segment driver board using shift registers. Simple, I know but a very useful design to me.

schematic:

[JuKu]

You are missing some findamentals. Read about bypass capacitors, how to route Vcc ang ground and about return currents. You want to route gnd and vcc first, with thick wires and close together. Also, your displays will all show the same number. Qh* is data out, which is Din to the next section.

[LEECH666]

Schematic rant: Overlapping text is bad. It makes a schematic look unprefessional and less neat. Try the smash function in Eagle to detach the component ref name from the symbol and move them to a spot where they don't overlap the symbols or other text while still maintinging that the name belongs to the symbol.

Cheers,
Florian

[olsenn]

Good work!

There will always be things you can do to improve a design, but your board works (I haven't verified anything) than the rest is just bonus.

[free_electron]

why use individual resistor ? switch to an array ! it makes routing and placing easier

[Christopher]

Schematic rant: Overlapping text is bad. It makes a schematic look unprefessional and less neat. Try the smash function in Eagle to detach the component ref name from the symbol and move them to a spot where they don't overlap the symbols or other text while still maintinging that the name belongs to the symbol.

Yep, the schematic took a few moments to do, I really just wanted to get the PCB done rather than the schematic. I'll redo it though .

You are missing some findamentals. Read about bypass capacitors, how to route Vcc ang ground and about return currents. You want to route gnd and vcc first, with thick wires and close together. Also, your displays will all show the same number. Qh* is data out, which is Din to the next section.

I feel like a fool for missing out bypass caps! Teacher says not to bother adding them, but I will anyway because it's good practice.

OH I knew that QH* pin was for something, I looked up a schematic quick and I didn't see it used.. I'll refer to the datasheet next time.

About the ground and vcc first, great tip! Seems so obvious now 

why use individual resistor ? switch to an array ! it makes routing and placing easier

I was going to use an array, but I thought it would have been a little difficult


Cheers guys, I'll redo the PCB with your hints in mind!

[digsys]

You've done a pretty good job with track angles but there are several junctions at right angles or worse !!
A good rule is - never have any track or join with a sharp angle. If you have a T join, chamfer them.
Don't make a V join, add a couple 45deg bends. It's not just for higher frequency, it's very impotant in the
etch process. Given the slow "data" rates, you can get away with a lot, but good practices are worth it.

[alm]

A good rule is - never have any track or join with a sharp angle. [...] Given the slow "data" rates, you can get away with a lot, but good practices are worth it.

Note that slow in this case means up to a few GHz. I would definitely recommend against right angle bends in microwave designs.

[Psi]

missing out bypass caps! Teacher says not to bother adding them

Does anyone else have an issue with this.

[digsys]

Note that slow in this case means up to a few GHz. I would definitely recommend against right angle bends in microwave designs

Not JUST GHz stuff. ANYTHING in the 50s+ MHz region is a WHOLE new ball game anyway, you need to pay a LOT more attention to track layouts.
GHz stuff is another voodoo entirely !! I've worked on GPS receivers ... yechh
I'm talking fast risetimes and standing waves issues. These happen at any data rate, and are more pronounced with faster chips ie HC
If you USE best practice ALL the time, irrespective whether it's necessary or not on a design, it a GOOD thing. Haven't even strated on EMI
emissions with right-angle tracks.

[digsys]

missing out bypass caps! Teacher says not to bother adding them ... Does anyone else have an issue with this

The teacher is full of KAKA. For a few lousy cents, it pretty much guarantees you WON'T have noise in / out issues in ANY
enviroment. Besides, once there are HC CMOS parts involved, it's a GIVEN, not an option. I've had MANY instyances of
intermittent faults traced back to insufficient decoupling !! And these are hard to pick somtimes, because .. " .. well it worked fine
for ages, but suddenly it's playing up ... " I often heard. It's part of best practice, and may even be an EMI issue anyway !!

[alm]

Note that slow in this case means up to a few GHz. I would definitely recommend against right angle bends in microwave designs

Not JUST GHz stuff. ANYTHING in the 50s+ MHz region is a WHOLE new ball game anyway, you need to pay a LOT more attention to track layouts.
GHz stuff is another voodoo entirely !! I've worked on GPS receivers ... yechh
I'm talking fast risetimes and standing waves issues. These happen at any data rate, and are more pronounced with faster chips ie HC
If you USE best practice ALL the time, irrespective whether it's necessary or not on a design, it a GOOD thing. Haven't even strated on EMI
emissions with right-angle tracks.

One (I believe) Japanese study measured the EMI effects of right angle bends and found them to be insignificant. Same for the impedance mismatch (less then the tolerance in track width using standard PCB processes I think). I don't remember what frequencies/edge rates they used, but it was much faster than 50 MHz. This is consistent with Howard Johnson's opinion on right angle bends.

[codeboy2k]

missing out bypass caps! Teacher says not to bother adding them

Does anyone else have an issue with this.

Yes. I do.

missing out bypass caps! Teacher says not to bother adding them ... Does anyone else have an issue with this

The teacher is full of KAKA. ...

The teacher is definitely giving you bad advice. Ask your teacher about SSO (simultaneously switching outputs) . 

Let's analyze. Assume one shift register is displaying a digit 8. (with the DP) ..  all the LED's are turned on, the device output ports are 11111111.

now, remember, all LED's will have a small capacitance, about 20pF maybe.

So you have a logic 1 out of the device, on each QA-QH, through a resister, charging a capacitor that is grounded through the common cathode. It won't take very long to fully charge the LED capacitance.

Now, at this point in time, assume you shift in all 00000000 to this device.  Now you have 8 bits that used to be logic 1, all switching to logic 0 at the same time. This is called a Simultaneously Switching Output (SSO), and is evil for EMI and ground bounce.. here's why.. When all 8 I/O pins switch from logic 1 to logic 0, this will quickly discharge all the LED capacitance through the device I/O pins, into the device, and out to ground via the device ground pin. Every single PCB trace, external device, bond wire, metalization, I/O pin, ground pin, solder pad, etc. from the LED capacitance to the ground (going through the device) will add a small inductance, and that inductance will cause the ground (as seen by the device!) to bounce quickly and return to zero at each switching of the outputs. And you don't need to be switching all 8 I/O's at once, even half as many, or even one, but the point is the LED display will be updating fast and switching shift register outputs fast and simultaneously.

This is ground bounce, and the di/dt of this bounce is what actually causes EMI. The bounce itself causes problems inside the device, because the device's view of the ground changes (i.e. ground comes up above ground momentarily)  This will often causes a small Vcc sag was well. 

The result of the ground bounce is that inside the device, signals that are normally referenced to ground can be misinterpreted because the ground is changing.

Bypass capacitors can provide the momentary current surge needed during the hi di/dt of the discharging capacitance (from the I/O pin to ground).

Now, you may get lucky and never run into a problem if you don't use bypass capacitors. But you will almost guarantee no problems when you do.

And that's why your teacher is full of kaka.

[digsys]

One (I believe) Japanese study measured the EMI effects of right angle bends and found them to be insignificant. Same for the impedance mismatch (less then the tolerance in track width using standard PCB processes I think). I don't remember what frequencies/edge rates they used, but it was much faster than 50 MHz. This is consistent with Howard Johnson's opinion on right angle bends

Luckily I don't rely on "other" peoples opinions much the time :-)  (but I DO study other peoples results, and if possible, test them).
40+ yrs of PCB design and my trusty high end Lecroys with FFT and EMI analysis show me otherwise.
I spent half my life fixing up "other people's opinions" :-) .. and failure analysis, sometimes in court.
There's never a shortage of opinions and studies ... evaluate them, and in the end YOU (OP) chose.

[jahonen]

One (I believe) Japanese study measured the EMI effects of right angle bends and found them to be insignificant. Same for the impedance mismatch (less then the tolerance in track width using standard PCB processes I think). I don't remember what frequencies/edge rates they used, but it was much faster than 50 MHz. This is consistent with Howard Johnson's opinion on right angle bends

Luckily I don't rely on "other" peoples opinions much the time :-)  (but I DO study other peoples results, and if possible, test them).
40+ yrs of PCB design and my trusty high end Lecroys with FFT and EMI analysis show me otherwise.
I spent half my life fixing up "other people's opinions" :-) .. and failure analysis, sometimes in court.
There's never a shortage of opinions and studies ... evaluate them, and in the end YOU (OP) chose.

If 90 degree turns are actually a bad thing, then how can we use any vias in a PCB? I remind you that we have not only one, but two 90 degree turns in each via we use

http://www.signalintegrity.com/Pubs/edn/bigbadbend.htm

Regards,
Janne

[Christopher]

Regarding the decoupling caps, I agree, I just forgot to add them . The teacher is an idiot yes, my knowledge far surpasses his (i'm also an idiot, still learning), but it's high school so it's understandable. He's still stuck with single sided boards with like 100 thou track widths max, I want to get the highest grade possible so I have decided to get the board professionally made with SMT parts. Lovely bloke though.

I'm going to integrate this schematic into my main board (Which will be controlling stepper motors, LCD, eeprom etc) so this was a useful exercise.

In future I'll be: routing gnd and power (And data) first, with larger track sizes and the most direct route, adding decoupling caps, making sure the angles are OK (I used a default option in Eagle for the majority).

Is putting a via on a SMD pad OK? bringing the wires out seems a little silly to me...

[codeboy2k]

Is putting a via on a SMD pad OK? bringing the wires out seems a little silly to me...

no vias in pads, unless you instruct the board manufacturer to cap them and plate over with copper. a via in the pad will wick away all the solder to the other side of the board and leave your component with little to nothing holding it on.

[free_electron]

Careful with Howard Johnsons statements ! He is right , but ....

1) he is talking about purely digital signals where you already have a large noise margin

2) talking about single signals. Differential or buses change the picture as the bend inserts delay and skew.... which he explains towards the end . The problem is most people only remember 'it doesn't matter', they forget the conditions.... Because they stopped reading halfway through.

3) the article is 12 years old... We are way beyond the rates he talks about. SATA, PCIX, Thunderbolt, push at triple to quadruple the speeds he talks about...

4) he talks about 8 mil traces... On a modern board with fine pitch FPGA we are going down to 3 mil track and gap ... And then manufacturing will start growling at you because the corners become an etchant trap... For pcb etching an inner corner should never be sharper than 90 degrees, 135 is preferred. In small features the sharp corners become etchant traps and there is a tendency to etch them open.... Try doing a flip chip board with 1.7 mil track...