What is the best layer for a groundplane?

[rklan]

Hello,

I am facing a serious problem choosing what layer of my multilayer PCB is the best to put a groundplane. Can someone advise me?


I often put the groundlayer on top, but yesterday I had a EMC-course, and the people overthere have another insight.
They say it is best to put it on an inner layer. They say, because it must be "unbroken"

Also they say NOT to use power planes, but just to route each trace needed for a power pin.
This is why (according to them): The power plane and the groud plane are exactly the same, for HF signals.
But, they need to be stitched needly together(for HF reasons) But you can't ( for DC reasons)
So it is better NOT to work with a powerplane.
Now I see the following advantages / disadvantages:

Groundlayer on top:

-Each smd pin for ground directly connected (adv)
-Ground layer broken by placing parts (dis)
-coupling of the return path in x-y direction uses less copper area (dis)

Groundlayer inner:

- Groundlayer more continious (adv)
- Not broken by placing parts (ground layer is running under the parts) (adv)
- every smd pin that needs a grn-level needs a via to connect to it (dis)
- coupling of the return path in z direction uses whole trace area (adv)


What do you think of these arguments? What is, in your experience, the best option?
I use smd parts and a micro running at 72 MHz.

Regards Remco Kleine

[mikeselectricstuff]

If you are going >2 layer, definitely inner layer to avoid breaks and  wasting placement space. You  don't want to be running signals in inner layers if you can avoid it as it makes track-hacking impossible.
There are always situations which need something different, but inner power and ground is the normal way to do it.
 I can't see any disadvantage in using a power plane in most circumstances - if nothing else it makes layout quicker.

There sometimes can be some very slight EMC and layout density advantages to putting power and ground on outer layers and signals inside but the fact that you very rarely see it done suggests that the downsides outweigh any advantages.
The only time I've ever seen it was on a large dense board with a lot of through-hole, as the smaller TH pads on inner layers allow more routing area.

[free_electron]

Right. Must not be a good course then.... 

First of all , there is no such thing as 'ground'. Ground is where people grow vegetables....
There is only a reference plane. Whether this is the positive or negative supply in you system does not matter. So yes, you can use a powerplane as reference just as you can use a 'ground' plane ( which is essentially the power supply return plane. Every electron ( conventional meaning, not electron meanin. Electrons in nature flow out of the negative pole and into the positive pole ) coming from the supply needs to go back to the supply.

Now, why do you want both a power and a ground plane... Because you have coupling between them. You are forming a capacitor that is dispersed through the board. This by itself will dampen high edge rate transients.

Rule number two : any outgoing signal needs a return path. The return path needs to be right underneath the outgoing path. Put a plane underneath and you dont need to worry .
Now, electrons do not always take the shortest route ! As edge rate increases they will lump together and actually follow the path underneath the signal trace.

Now, are we going for emc or signal integrity ? The two are related , but NOT the same !
For emc. One plane is ok , it is a shield. Fir signal integrity .. It is important. And signal integrity problems can cause emc problems...just as emc problems can cause signal integrity problems

I mentioned edge rate. It is not the frequency of a signal that is important but its edge rate.how to explain.. Take a surface of water , unlimited in size. You are in the middle and you create ripples.( sinewaves ) you can make slow ripples, or fast ripples. They will propagate smoothly. Put a wall in the water and when the clean waves hit they will create foam and breakers. If the amplitude of the waves is larger you get more splattering when they hit the wall. This splattering causes emc problems. Energy is scattered all over and lots of new frequencies are created ( large drops, small drops ). This is an emc problem. You are dispersing energy in the frequency spectrum. It is also a signal integrity problem. Your nice clean sinusoidal waves are now pure anarchy.

There will be waves reflected back and they will intermodulate with outgoing waves. If you throw a stone in water you will see concentric circles. When they hit the shore they bounce back.. This is signal reflection. The reflected energy intermodulates iwth ougoing energy.... Signal integrity problem.
This not an emc problem.

What is edge rate. Take a piece of paper lined with squares.
Draw a sine wave, 10 squares peak to peak and 20 squares long.
In this same 10x 20 area draw a triangle wave. And finally draw a square wave.

Now look in every square at the dv/dt. How many volt per second do i get.
For the triangle wave this is always constant. The slope of the signal is always 45 degrees in a square. Dv dt is a constant ( apart from the peak where you change direction )
Look at you sinewave. Here the dv dt is not a constant. If you are close to the midpoint you rize fast. When approaching the peak it slows down... Take a look at the square wave.. The dv dt is off the chart.

That is edge rate : how fast do we climb per time unit. Higher edge rates will radiate. Even the slightest mismatch will cause trouble, both for emc and integrity.
Back to the water model. Tsunami. An earthquake causes part of the ocean floor to drop or raise in a very short time. This 'thump' is not a sinewave but essentially a square wave. Result : immense waves that crash on the shore causing devastation. There is your problem.

Now, your cpu there will for sure use square waves, but any fast cpu or chip these days has edge control built in. We ( when i say 'we' i mean chip designers , as i am in the semiconductor design business) limit the current that can flow in and out of a pin. So our i/o structures have an impedance. That coupled with the capacitance between signal trace and reference plane ( see how i cleverly avoided the usage of 'ground' here ) forms an rc filter.

It does not matter if the capacitor sits to power or return plane. Sometimes we switch high to low , sometimes low to high. Sometimes it is the transistor between power and io , ,sometimes the transistor between io and return that energizes. Charge is displaced, energy flows.

Keep in mind that what i say here are abstractions and simplifications. Everything is governed by maxwells laws . And , as edge rate increases the field interactions become very difficult. Thats why we have tools for such cases. Hyperlinx , avct and others. Those are 3d field solvers and can show you the problem area's

Back to your problem. Ideal is a 4 layer board. With an even spacing between the layers. You need to know that also the layer stack is important.
Bards are made around a core doublesided board and layers are added.
So , do we start with a thick core and add two thin layers ? Or do we start with a thin core and add two thick layers... Or do we make all layers the same thickness...

This depends on the impedance you want to create. Any discrepancy in impedance will create 'breeakers' an impedance change is like a stone wall in the water. Some waves hit it , some go around the edges, some refelct. You don't want walls... You don't want impedance changes.

Impedance on a board is determined by the distance beteen a signal trace and its return path , and the material used ( dielectric constant ) you need to know the constant, the thickness of the isolator and the output impdance of an io pin ( typically around 22 ohms). And then you can calculate the required width of the trace for impedance matching. If this width becomes absurdly wide you can decrease the distance between signal and return path.

So yes, you need to tune the psb stackup. You will have to talk with the board house what prepreg material thcikness they have....

For you 72MHhz chip... Not so much a problem. The fun begins at roughly 200 MHz... At 500Mhz you need impedance control, striplines etc, push it above 1GHz and even that doesnt work anymore. You need differential signaling then .. Note that it is not the absolute frequency but the edge rate that is important, but as frequency goes up, edge rate has to go up to. You cannot make a 5 volts 1 ghz signal with and edge rate of 1 volt per second ...

Did i confuse you ? Good! You passed with flying colors and can now enter the hall of people who have been taught the emc signal integrity course. You will be perpetually pondering on all theses aspects and whatever fun you had with electronics is forever ruined by the unanswered questions.

There is only one valid answer to all questions on how to design a system for emc and signal integrity.... And that answer is 'it depends' ...

[Neilm]

Right. Must not be a good course then.... 
.....
Did i confuse you ? Good! You passed with flying colors and can now enter the hall of people who have been taught the emc signal integrity course. You will be perpetually pondering on all theses aspects and whatever fun you had with electronics is forever ruined by the unanswered questions.

There is only one valid answer to all questions on how to design a system for emc and signal integrity.... And that answer is 'it depends' ...

One of the best explanations of EMC I have read for a long time. I just wish some of the engineers I work with would read it...

Neil

[ejeffrey]

The simplest reason for the standard way: power and ground on the inside means signal traces on the outside, which is good for probing and rework.  If your prototype has one buildup, you don't want to change it for production!

[rklan]

Thanks a lot Guys!!
I am convinced now to place my reference plane(s) on the inner layers.
Thanks for the advice and the backgrounds.
This forum is really great!!

Regards Remco

[richcj10]

Just for a refrance,

I allways put power and gnd on the inner layers of the PCB's. I usaly have 3v and 5v. So I usaly go (top to Bottom) Sig, 3v, gnd, 5v, sig. I once had a client go bonkers and wanted "shealding". So, I gave it to him with a sig, gnd, 3v, gnd, 5v, gnd, sig. A $100 a piece 7 layer board was made. lol

[knoppix47]

@richcj10
So i have low voltage signals in a very noisy environment. Can is go  GND, sig, GND, 3V? Or why do you put your signals on the outside?

[Wilksey]

What free_electron said!

I use the top and layer 2 on a ML board for the signal / reference, unless I need to route on other layers, then it depends on the stack-up and any impedance requirements.

If I route any controlled traces on the bottom i'll use the layer before the bottom for ground.

I have no idea if the way I do it is "correct" or whatever, but I have never had any failures that down to that arrangement, and some of my stuff has gone through EMC.

[neil t]

Right. Must not be a good course then.... 

First of all , there is no such thing as 'ground'. Ground is where people grow vegetables....
There is only a reference plane. Whether this is the positive or negative supply in you system does not matter. So yes, you can use a powerplane as reference just as you can use a 'ground' plane ( which is essentially the power supply return plane. Every electron ( conventional meaning, not electron meanin. Electrons in nature flow out of the negative pole and into the positive pole ) coming from the supply needs to go back to the supply.

Now, why do you want both a power and a ground plane... Because you have coupling between them. You are forming a capacitor that is dispersed through the board. This by itself will dampen high edge rate transients.

Rule number two : any outgoing signal needs a return path. The return path needs to be right underneath the outgoing path. Put a plane underneath and you dont need to worry .
Now, electrons do not always take the shortest route ! As edge rate increases they will lump together and actually follow the path underneath the signal trace.

Now, are we going for emc or signal integrity ? The two are related , but NOT the same !
For emc. One plane is ok , it is a shield. Fir signal integrity .. It is important. And signal integrity problems can cause emc problems...just as emc problems can cause signal integrity problems

I mentioned edge rate. It is not the frequency of a signal that is important but its edge rate.how to explain.. Take a surface of water , unlimited in size. You are in the middle and you create ripples.( sinewaves ) you can make slow ripples, or fast ripples. They will propagate smoothly. Put a wall in the water and when the clean waves hit they will create foam and breakers. If the amplitude of the waves is larger you get more splattering when they hit the wall. This splattering causes emc problems. Energy is scattered all over and lots of new frequencies are created ( large drops, small drops ). This is an emc problem. You are dispersing energy in the frequency spectrum. It is also a signal integrity problem. Your nice clean sinusoidal waves are now pure anarchy.

There will be waves reflected back and they will intermodulate with outgoing waves. If you throw a stone in water you will see concentric circles. When they hit the shore they bounce back.. This is signal reflection. The reflected energy intermodulates iwth ougoing energy.... Signal integrity problem.
This not an emc problem.

What is edge rate. Take a piece of paper lined with squares.
Draw a sine wave, 10 squares peak to peak and 20 squares long.
In this same 10x 20 area draw a triangle wave. And finally draw a square wave.

Now look in every square at the dv/dt. How many volt per second do i get.
For the triangle wave this is always constant. The slope of the signal is always 45 degrees in a square. Dv dt is a constant ( apart from the peak where you change direction )
Look at you sinewave. Here the dv dt is not a constant. If you are close to the midpoint you rize fast. When approaching the peak it slows down... Take a look at the square wave.. The dv dt is off the chart.

That is edge rate : how fast do we climb per time unit. Higher edge rates will radiate. Even the slightest mismatch will cause trouble, both for emc and integrity.
Back to the water model. Tsunami. An earthquake causes part of the ocean floor to drop or raise in a very short time. This 'thump' is not a sinewave but essentially a square wave. Result : immense waves that crash on the shore causing devastation. There is your problem.

Now, your cpu there will for sure use square waves, but any fast cpu or chip these days has edge control built in. We ( when i say 'we' i mean chip designers , as i am in the semiconductor design business) limit the current that can flow in and out of a pin. So our i/o structures have an impedance. That coupled with the capacitance between signal trace and reference plane ( see how i cleverly avoided the usage of 'ground' here ) forms an rc filter.

It does not matter if the capacitor sits to power or return plane. Sometimes we switch high to low , sometimes low to high. Sometimes it is the transistor between power and io , ,sometimes the transistor between io and return that energizes. Charge is displaced, energy flows.

Keep in mind that what i say here are abstractions and simplifications. Everything is governed by maxwells laws . And , as edge rate increases the field interactions become very difficult. Thats why we have tools for such cases. Hyperlinx , avct and others. Those are 3d field solvers and can show you the problem area's

Back to your problem. Ideal is a 4 layer board. With an even spacing between the layers. You need to know that also the layer stack is important.
Bards are made around a core doublesided board and layers are added.
So , do we start with a thick core and add two thin layers ? Or do we start with a thin core and add two thick layers... Or do we make all layers the same thickness...

This depends on the impedance you want to create. Any discrepancy in impedance will create 'breeakers' an impedance change is like a stone wall in the water. Some waves hit it , some go around the edges, some refelct. You don't want walls... You don't want impedance changes.

Impedance on a board is determined by the distance beteen a signal trace and its return path , and the material used ( dielectric constant ) you need to know the constant, the thickness of the isolator and the output impdance of an io pin ( typically around 22 ohms). And then you can calculate the required width of the trace for impedance matching. If this width becomes absurdly wide you can decrease the distance between signal and return path.

So yes, you need to tune the psb stackup. You will have to talk with the board house what prepreg material thcikness they have....

For you 72MHhz chip... Not so much a problem. The fun begins at roughly 200 MHz... At 500Mhz you need impedance control, striplines etc, push it above 1GHz and even that doesnt work anymore. You need differential signaling then .. Note that it is not the absolute frequency but the edge rate that is important, but as frequency goes up, edge rate has to go up to. You cannot make a 5 volts 1 ghz signal with and edge rate of 1 volt per second ...

Did i confuse you ? Good! You passed with flying colors and can now enter the hall of people who have been taught the emc signal integrity course. You will be perpetually pondering on all theses aspects and whatever fun you had with electronics is forever ruined by the unanswered questions.

There is only one valid answer to all questions on how to design a system for emc and signal integrity.... And that answer is 'it depends' ...

Interesting lesson, thanks.
regards Neil

[vealmike]

Very good stuff.

My day job is moving data around in the multi GHz range. Free-electron has given a very good intro. to the subject.


I think a little more emphasis should be placed on return paths. Every signal will induce a current in it's reference plane. Even perfectly balanced diff pairs do this (Yeah, I know you were taught that they didn't  .)

Because there will always be a physical separation between signal and return current, it is always possible to take an imaginary 2D slice of the structure and calculate the area of the loop in which the current flows. Currents flowing in loops have inductance proportional to the loop area, they make good electromagnetic radiators.

When routing for EMC (and SI) it's important to route not just the trace, but the return current too. Your signal should (ideally*) never cross splits in the reference plane eg a signal referencing GND should cross a plane split and reference 3V3.
If your signal hops up a layer in a multilayer PCB then this usually means that you need a reference plane stitching via in the area of the signal via.



72MHz isn't normally considered high speed. But radiation will affect a VHF radio so it's worth thinking about.

Lastly, there's a reason most people use reference plane and GND interchangeably, GND is usually used as the ref plane as every chip on your PCB will usually be hooked to the same GND. Where a signal couples two chips with differing supply voltages and a shared GND, then the GND is the obvious choice for a ref plane. I guess most of us also find it easier to visualise a return current flowing in a GND than they do in a power plane. Truth is, the return current doesn't much care.

If you really want to learn about this, get a copy of Black Magic by Howard Johnson. It's not black magic, it's perfectly understandable but don't tell anyone. It's a lucrative niche.


* Sometimes, on a budget its impossible not to have signals cross reference planes. Use a capacitor to couple the planes at the point that the signal crosses but don't expect to get away with this in the GHz range.

[nctnico]

Where a signal couples two chips with differing supply voltages and a shared GND, then the GND is the obvious choice for a ref plane. I guess most of us also find it easier to visualise a return current flowing in a GND than they do in a power plane. Truth is, the return current doesn't much care.

True but if you change layers (reference planes) the capacitive coupling between the planes won't be enough for the return current for high speed signals (SATA, PCI express). You'll need to add a capacitor (say 10nf in size 0603 or preferably smaller) very close to the point where the signal crosses from one plane to the other.

[T3sl4co1l]

Reserve about half the layers for solid ground plane.  Half of these, in turn, can be supply rails.  (Depending on PCB design approach, and what tool you use, it may be constructed from polygons, fills, planes, or etc.  Doesn't matter, as long as it's a lot of solid copper.)

Two layer board: half of two is one, so one layer gets solid ground.  Route all supplies.

This has the special case where, because you don't have anywhere else to go, you must interrupt the ground pour with traces that need to jump under top-side traces.  This is fine.  You make up for it by pouring the top side too, which must be ground (don't pour one side supply and one side GND -- both planes will be hopelessly chopped up from all the traces).  Stitch the two pours together, so that ground is contiguous around any splits in the planes.

Four layer board: half of four is two, and half of two is one.  So you can reserve one layer for ground, one for supply (which can be one dominant supply, or divided into many supply regions if you like), and route the rest.

Note: avoid tight rows of vias, because these will break the internal planes.  Allow some space between groups of vias.

You would normally set the planes on the inside, because that leaves the outside layers for routing and placement.  EM performance is quite fine, because the planes are close to the surface (in the typical proto PCB build).

Six layer board: half of six is three, and half of three isn't whole, so you have some options here.  You might use two ground planes and one supply, or one ground and one supply and use the extra layers for routing.

A typical stackup is:
Top
GND
Inner Routing 1
Inner Routing 2
VCC
Bottom

The inner routing layers are fully shielded, so you can get excellent signal quality on them.  They are also stripline, which isn't dispersive like microstrip (outer layers) is.

Or you can put the GND/VCC in the middle, and get microstrip and buried microstrip on the outer layers; this isn't good for signal quality (the outside layers have more distance to the planes), but can be handy for routing circuits with minimal trace lengths.

8+ layers:

You'd typically do this for a high speed, high density computer board, where you need to route many supplies (at least two) and signals into BGA components.  Combined with buried vias (if you can handle the expense), this can do amazing things for density and high speed design.

Tim