When can you have too many vias?

[jdraughn]

I'm in the process of designing a motor controller board using surface mount mosfets and a DRV8704. When I'm adding vias to conduct heat and current between the top and bottom layers, is it possible to have too many? Do the board manufacturers have a limit? I was originally going to go through OshPark, but the board size has gotten to the point where I might as order through someone like Elecrow, and not worry so much about keeping the size of the board down as tiny as possible to keep the cost down. I looked and didn't see anywhere on OshPark's website that mentions a limit on vias.

[KE5FX]

If your PCB house isn't whining about how many vias they have to drill, that means you should add some more. 

[Kjelt]

Too many? It is better to make sure they are the right size and located on the right spot.
Read this topic and the links in them, very interesting research about what size the vias should be and their position and seperate soldermask stencil layout for the paste in order to prevent solder wicking and lack of solderpaste (holes) beneath the thermal pad during reflow:
https://www.eevblog.com/forum/eda/why-is-the-footprint-of-the-thermal-pad-so-small-on-this-ic/msg1277123/#msg1277123

[jdraughn]

Too many? It is better to make sure they are the right size and located on the right spot.
Read this topic and the links in them, very interesting research about what size the vias should be and their position and seperate soldermask stencil layout for the paste in order to prevent solder wicking and lack of solderpaste (holes) beneath the thermal pad during reflow:
https://www.eevblog.com/forum/eda/why-is-the-footprint-of-the-thermal-pad-so-small-on-this-ic/msg1277123/#msg1277123

Yep, I had read that, but even if they are the right size, and in the right spot, I was wondering if you could have too many.

[Rerouter]

As long as you have a reduced set of drill holes on your board, they generally wont complain for normal full through vias. e.g. if you can reduce your board to 3-4 drill sizes, they can generally drill 50 holes in the time it takes to park the head and swap to another drill size.

E.g. almost all of the cheap services claim a 0.3mm hole minimum for vias, so the most common drill size for them will likely be 0.3.

[Roeland_R]

I'm in the process of designing a motor controller board using surface mount mosfets and a DRV8704. When I'm adding vias to conduct heat and current between the top and bottom layers, is it possible to have too many? Do the board manufacturers have a limit? I was originally going to go through OshPark, but the board size has gotten to the point where I might as order through someone like Elecrow, and not worry so much about keeping the size of the board down as tiny as possible to keep the cost down. I looked and didn't see anywhere on OshPark's website that mentions a limit on vias.

when your pcb is beginning to feel flexible you might have too many vias.. [emoji41]

[Kjelt]

Yep, I had read that, but even if they are the right size, and in the right spot, I was wondering if you could have too many.

Ah ok, well there are ofcourse some DRU rules stating the minimum distance between vias to which your design should comply.
But I can not find a max of drill holes in a design as there was in the past, but to make sure check on forehand with the fab you selected to ask if the nr of via's you used is ok for production.

[KE5FX]

In RF or high frequency SMPS you may want to shape current path hence you may not want to put too many vias, also sometimes too many vias makes soldering very hard and reduces overall system reliability.

There is no case where adding another plane-stitching via will make things worse from an RF perspective.  The more your board looks like a monolithic slab of copper, the better.

What can cause problems is inadvertent construction of a parasitic filter structure through overly-consistent via placement.  That's hard enough to do on purpose, and not likely to happen by accident.  If you think it may be happening, scatter a few more vias at random, and/or create multi-rank fences of vias with different spacing characteristics.

[T3sl4co1l]

There is no case where adding another plane-stitching via will make things worse from an RF perspective.  The more your board looks like a monolithic slab of copper, the better.

What can cause problems is inadvertent construction of a parasitic filter structure through overly-consistent via placement.  That's hard enough to do on purpose, and not likely to happen by accident.  If you think it may be happening, scatter a few more vias at random, and/or create multi-rank fences of vias with different spacing characteristics.

I would simply refine the first sentence:

There are cases where it may: for example, a trace crossing an inadvertent cavity, formed by top and bottom ground pour and unlucky placement of vias.  If the signal in the trace is, say, 5GHz, and the cavity's resonances are 3 and 9GHz (give or take, plus other modes), then adding some vias in certain locations could raise the resonance to 5GHz, causing a null in that trace's response.

So, that said, there may be cases where a dubious design gets worse from more via stitching.  But there is no case where an already-good design gets worse.

That is, the cavity / waveguide resonances can only be pushed to higher and higher frequencies, by adding more vias: once all modes, in all locations, are above the highest signal harmonic frequency, the design meets the minimum requirement for stitching.

(Stitching can still be improved from there, because leakage occurs between regions, even below the cutoff frequencies of those regions.  This manifests as electric or magnetic coupling -- field leakage -- in the near field, or evanescent (internal and surface) waves, in the far field.)

I can think of another case where it would get worse, but it's a special case: using the ground return path as series inductance.  For instance, in a switching inverter, the series inductance to a MOSFET source pin can be used to limit dI/dt and set the switching loop impedance.  If the path is intentionally made long, the inductance can become useful (1-100nH is pretty practical).

These sorts of things are better implemented using explicit planar inductors, or net bridges, rather than being drawn in copper purely by coincidence.  Because, consider what would happen to your perfectly tuned design, if, down the line, a less experienced layout guy modifies it -- "oh, this ground is flapping in the breeze, let's stick some vias in there, that'll surely make it better!" -- and then it blows up emissions at 300MHz or something! 

Tim

[Bud]

I once read in a paper that putting too many vias will or may change the dielectric constant of the substrate.
But do not know what other conditions must exist in order for this becoming a problem from practical view if it happens.

[KE5FX]

There are cases where it may: for example, a trace crossing an inadvertent cavity, formed by top and bottom ground pour and unlucky placement of vias.  If the signal in the trace is, say, 5GHz, and the cavity's resonances are 3 and 9GHz (give or take, plus other modes), then adding some vias in certain locations could raise the resonance to 5GHz, causing a null in that trace's response.

Yeah, that's sort of a subset of the parasitic-filter problem.  Some of the gurus recommend randomizing the placement of ground vias for that reason, so that no modes get a chance to dominate.  But it's a hard habit to pick up when I'm already in OCD-land during the layout process.

[T3sl4co1l]

Yeah, that's sort of a subset of the parasitic-filter problem.  Some of the gurus recommend randomizing the placement of ground vias for that reason, so that no modes get a chance to dominate.  But it's a hard habit to pick up when I'm already in OCD-land during the layout process.

Heh, I break that by using a different rule: instead of grid alignment necessarily, I tend towards error diffusion.  Keep the average distance between vias constant.  Revel in the pattern having a more abstract beauty, like leopard patterns instead of plaid.

Tim

[PCB.Wiz]

When I'm adding vias to conduct heat and current between the top and bottom layers, is it possible to have too many?

I'll add to your confusion by suggesting Paste Vias - these are Vias, with a paste mask so they (mostly) fill with solder.
Under a thermal PAD you tend to get paste in via naturally, but outside the IC footprint you can also add more vias...
The air-path is by far the highest thermal resistance, so all of this effort only make the PCB temperature more even

[mash107]

when the price is outrageous. PCB fabricators don't whine... they just charge you more

What matters more is limiting the number of unique drill sizes

[vealmike]

Yes, there is a case when adding more vias causes harm.

Every via will create an antipad on planes that it doesn't connect to.
If you're not careful, vias placed close together will create holes and slots in the planes. This causes IR drops for power currents.

It also forces return currents for high speed signals to travelling around the void rather than following the signal current.

If you have a high speed signal, there will be a current in the trace as the signal changes. There will be an equal and opposite current in the power plane that the signal references (usually the closest plane).

Anytime you increase the loop area around which a current flows, you increase inductance. So creating slots under high speed signals will make your board radiate and will give signal quality issues.

[T3sl4co1l]

Yes, there is a case when adding more vias causes harm.

Every via will create an antipad on planes that it doesn't connect to.

Excellent point, multilayer boards with thru vias!

Also, the radiation of all those holes, for RF boards (say for a board with analog stuff on one side, RF on the other, and using the inner planes as shielding between them).  No, the holes won't radiate much (as long as wavelength >> dia), but there's still a small amount of coupling, and it adds up -- it can spoil your FCC/CE rating very easily, if you aren't careful!

(If you need a shitton of vias, try to keep them between layers, and use blind/buried vias or HDI... if you need the vias more than you need the bucks $$$ that is! )

Oh and, you can increase the density a little bit, by removing the inner layer pad (for inner layers poured with a polygon) -- but, don't reduce the clearance too much, because the board house depends on a large clearance (10 or 20 mils) for drilling.  All the tolerances add up, when they laminate and drill the board.  They will complain if you push it too tight!

Tim

[KE5FX]

Yes, there is a case when adding more vias causes harm.

Every via will create an antipad on planes that it doesn't connect to.

Excellent point, multilayer boards with thru vias!

That's why I specified plane-stitching vias.   Yes, if you create cavities and break return paths, even one is too many.  Use them to make your board look more monolithic, not less.

[jdraughn]

OP here. Here is a screenshot showing a directFet with lots of .012" vias. Too many?

[Kjelt]

are you looking for air cooling 

[T3sl4co1l]

OP here. Here is a screenshot showing a directFet with lots of .012" vias. Too many?

Likely.  Expect fab complaints or poor results, and poor soldering.

Fabs usually limit the hole spacing (edge to edge) to >10 mils.  I'm not sure that that's been observed (but it's hard to tell from a picture).

Tim

[jdraughn]

The hole spacing on the via's passes OshPark's DRC. So how many via's do you think I should remove so I won't likely get any complaints or poor results from the fab? 50%?

Thank you for taking the time to offer your advice.

[KE5FX]

Yes, that's certainly over the top.  There should be some guidelines for heat dissipation in the FET's data sheet, or possibly in separate application notes published by the manufacturer.  Have you had a look for those?

If nothing else, you don't want holes in your solder pads.  You will need to have them filled and/or plated over if you want to do that.  It'll be cheaper to create a checkerboard pattern with solder mask and put the vias in the masked areas only.

[T3sl4co1l]

A few vias are okay, but going nuts will suck solder away.  I try to use 8 to 12 mil i.d. vias, which wick less than larger ones do (particularly in lead free reflow).  When a large pad is present (e.g., QFN center pad), there may be enough extra solder (on the order of 1-2 mils height) to give some headroom as far as wicking (you can calculate how many vias are needed to suck up that excess, assuming they all fill, and use that as the absolute maximum count).

If you need absolute maximum cooling, filled or plugged vias, or HDI (usually laser drilled and plated shut), is what you need.

DirectFETs are made to be cooled with a heatsink, so you shouldn't need much anyway.

Tim

[jdraughn]

I have listened and I reworked it. That first picture was only semi-serious, I figured it had to be too much, but wanted to hear what experience had to say.  Here is new picture. Is there still obviously too many vias?

[T3sl4co1l]

You'll have better switching performance if you do the tight layout on the top layer and leave the bottom solid ground plane (and as little routing as possible).

The distributed vias don't do anything.

If you well and truly can't afford 2oz+ copper, at least clamp the board between aluminum plates with thermal pads.  That will accomplish about an order of magnitude than any density of vias will.

If you want to get obsessive about copper, pours and vias, you can always whittle the thing out of copper sheet.  It'll keep your OCD better occupied, too.

Tim