You've also kindly made my point for me, high speed digital design is a great use of SI, using it for everything all the time is not.
And you'd be wrong. Crosstalk can become an issue even in low-speed designs. The classic example is reset line which goes along some signal line with sharp edges, and in certain conditions enough of a signal can couple into reset line to trip the processor into reset. I've seen few boards which have this problem, and one of those was designed by no other than yours truly - that was back when I, just like you are now, thought that crosstalk is only a problem for high-speed lines. Well, I learnt that lesson the hard way
If you don't want to repeat my mistake (with literally weeks of debugging and banging my head against the wall before I was able to figure out what the problem was), I'd recommend you to pay attention to this problem. This is especially so if you use modern low-power low-Vcc devices, as the lower the interface voltage, the lower the gap is between logic zero and one, and less of a crosstalk is required to trip the circuit. You can actually calculate crosstalk using free Saturn PCB Toolkit - play around with it, and you will see it doesn't take that much to cause problems, as modern chips have very sharp edges, even cheap STM32F4 MCUs can output signals with rise time of only 2.5 ns, more advanced MCUs and pretty much all FPGAs can reach sub-nanosecond rise times.
Just for reference, at 3.3 V Vccio and typical 1.6 mm two layer FR4 PCB (Er=4.6), for 1 ns rise time signal it takes less than 10 mm of coupled length at 0.25 mm apart to have 3.2 V crosstalk spike in adjacent trace, for 2 ns the coupled length is 15 mm for the same spike, for 5 ns rise (which AFAIR even atmega328p can reach) you need about 40 mm of coupled length. As you can see, it doesn't take all that much to cause issues which are going to be *extremely* hard to debug because presence of debug probe and even your hand will change the behavior (because it will change load capacitance of the trace).