World's worst QFN

[Daixiwen]

I remember a while ago seeing this twitter post on the world's worst QFN ever:
https://twitter.com/whitequark/status/1106970233485561858



I had a good laugh back then, wondering who would be masochist enough to use that.


...

Well guess who is going to implement that component on a PCB now... 

[Ysjoelfir]

Don't forget to add the cry for help or some kind of ragequit on the silkscreen layer. Right above the "Detail B" arrow line would be sufficient space. But remember to mirror the text - this is the bottom view.

[coppice]

I guess a BGA could be considered the world's worst QFN. 

[Ysjoelfir]

I would prefer to create a footprint of more or less any standard bga over THAT thing. A BGA is usually at least consistent in spacing and pin numbering.

[ataradov]

This seems like it is designed for easy fan out. It is annoying to create the footprint, of course, but you only have to do that once.

[Daixiwen]

It's an application where we can't use BGA's. It's a very low volume PCB and with very expensive components so we'd better get it right on the first try!
It's probably designed this way for easier fanout but there are still a few things I don't get... some differential pairs (but not all) use an oblong pad for one of the signals, and a round one for the other one. And there are 38 unconnected pads. Because of course.
The pin used to hold the chip in powered down state is called COMA_MODE. Probably a good description of the layout engineer when he is finished creating the footprint!

[Berni]

Just as I recovered from PTSD from A3P250-QNG132, now I can't unsee this.

And when i thought those dual row QFNs ware evil here you show me a tripple row QFN.

Attached is what blueskulls evil chip looks like.

[Daixiwen]

 

[daqq]

This is becoming silly. At some point we're gonna have to add another package name to the list, namely "Other", "Arbitrary" or "Because f*ck you, that's why!".

[RoGeorge]

Rookie complain, those chips were meant for vertical mounting.   

[babysitter]

Pure pr0n.

[EEEnthusiast]

Who did that vertical mount? the technician is pure genius

[nctnico]

Rookie complain, those chips were meant for vertical mounting.   

That is pure art! 

[mariush]

re the image in first post... it looks bad, but in reality it's not THAT bad. 

If you pay attention you'll notice it's mirror image (left and right sides, top and bottom), with just some pads being elongated to be 2x the size or something like that.
So you only have to get a quarter of that footprint done and then mirror it twice and then extend some pads and you're done.

[T3sl4co1l]

Worst one I've used, not all that bad but still worthy of an appropriate library name:



3D view in situ: https://www.seventransistorlabs.com/Images/AltiumPlacement.png

Tim

[Nominal Animal]

Rookie complain, those chips were meant for vertical mounting.   

  I am at loss for words.

[EEEnthusiast]

Worst one I've used, not all that bad but still worthy of an appropriate library name:



3D view in situ: https://www.seventransistorlabs.com/Images/AltiumPlacement.png

Tim

This one is still OK. Looks symmetric and organized. Not like the random pins of various sizes placed at arbitrary locations. Someone has to be given a nobel prize for these kinds of pinout.

[Rerouter]

I can handle the really weird pinouts, I hate the stupid assignment of some chips much more,

Oh, you have a 16 bit port left exposed, intended for interfacing to external memory, LCD's or similar, Why... why do they split those pins up as much as humanly possible. the I/O is sequential, so why is this function shotgunned around the pinout... or serial ports with RX half the chip away from TX....

[exe]

Do you guys draw these components by hands? I wish manufacturers release components as well. To me it feels quite a waste of time and effort to try to replicate what was already done.

The worst part for me is to calculate sizes and distances when only a few dimensions are given. There is also a risk of doing it wrong.

[EEEnthusiast]

Most component manufacturers provide footprint data in multiple format these days. So that makes life easier...

One thing I have learnt from QFN parts with different sized pads is that if the centre pad is very large and if the solder paste on that pad is not split into different sections, there is a finite risk of the outer pads not making contacts. This is due to the surface tension of the molten solder causing the package to lift up.

The best option is to split the QFN centre pad to smaller pads so that the footprint can also be split.That makes soldering reliability much better.

[TheUnnamedNewbie]

I suspect the reason they don't (always, some manufacturers do release footprints) is
a) everyone uses different standards and methods of drawing components. So even if they do release components a lot of people don't use them. I have this issue with schematic symbols mostly - some people like drawing schematic symbols as one big block, others like splitting them up. How do you think you should split them up? What pitch between pins? What grouping? etc etc
b) You can't always support every single package out there.
c) footprints tend to change based on technology too - soldermask openings, pad size, hole sizes, how you do your silk, etc.

The worst part for me is to calculate sizes and distances when only a few dimensions are given. There is also a risk of doing it wrong.

I do wish the vendors gave me a list of coordinates for each pad sometimes - would be real convenient. What is even worse is if they give all values, but in the 'wrong way' so I need to do the math to convert it to the way I need to imput the data into altium footprint generator or whatever.

[Daixiwen]

I suspect another reason they don't give ready made footprints is that they don't want to be held liable in case of manufacturing problems.
I wonder too how the central pad will affect soldering of the other pads, especially with so many rows all around.
Worse case, we finish the soldering process with a heat gun and a hammer 

[radar_macgyver]

Well mine is minor compared to some of these examples, but I was forced to re-spin a board because I used the TPS7A4700, which comes in a QFN20 - with 0.65 mm pad spacing instead of the usual 0.5 mm.  Oops.

[GeorgeOfTheJungle]

FAB: Do you want additional interconnect layer(s)?
client: No, thanks.
FAB: Ok, don't move the pads around then.
client: fine.

Routing that isn't gonna be any worse than say, any Intel bga, no?

[ebastler]

Rookie complain, those chips were meant for vertical mounting.   

We had this picture before (https://www.eevblog.com/forum/chat/qfn-dead-bug/msg2338626/#msg2338626), but I have not figured out the original source yet. Google image search finds various Twitter posts and other obscure channels. "PS3 hacking" is mentioned somewhere. Does anyone know where/when/why/by whom this was done?

Edit: Ah, this seems close to the source:
https://www.psdevwiki.com/ps3/Syscon_Hardware