Xilinx FPGA decoupling cap layout (traces and vias)

[learnfromfailures]

I have the decoupling capacitors located close to Spartan 7 (<2000 mil). I'm trying to route these and connect it to the BGA pin. According to xilinx UG393, I shouldn't use same vias.

PCB layout engineers often try to squeeze more parts into a small area by sharing vias among multiple capacitors. This technique should not be used under any circumstances. PDS improvement is very small when a second capacitor is connected to an existing capacitor’s vias. The capacitor mounting (lands, traces, and vias) typically contributes about the same amount or more inductance than the capacitor's own parasitic self-inductance.​

[/i][/b]

I'm trying to connect them using single trace and then add a via to touch the 3.3 V power plane. I don't think this will induce any additional parasitic inductance. I'm placing a via perpendicular with short trace. Is this correct ? Or do I need to add separate vias to each cap.

[nctnico]

If CFGBVS is a power supply rail then I strongly suggest to make it a copper pour on an inner layer. Where it comes to vias: I like to connect all capacitors together on the top or bottom layer (depends on where they are mounted) and then have 1.5 to 2 vias per capacitor. And what size are the capacitors? 0603? If so, then I'd go for 0402 otherwise the traces won't fit.

[learnfromfailures]

The caps are 0805. Yes, I have CFGBVS are power 3.3V plane. I'm planning to connect the cap with via (minimum traces) to the plane and do the same with FPGA using microvia to the power plane.

Here is the answer. (connecting Cap to Planes)The wider the trace, the lower the inductance. The same goes for connecting component pads to planes. For each additional via (multiple vias in a pad), inductance will be reduced. The capacitance between the power and ground planes can also be very useful for decoupling when placed physically close together.

(connecting Component lead to cap) : Regardless of whether the PCB is simple or complex, almost all products require a trace to be present between a component lead and capacitor, or interconnect via. This interconnect trace, also identified as pin-escape, breakout, and similar terminology. A trace must be routed from the component to a via located nearby for connection to a signal, power, or ground plane. It is not possible, manufacturing wise, to have large vias embedded in a component's mounting pad. Solder may flow into the via, preventing the component from having a secure bond connection in addition to other manufacturing concerns

I got this from chapter 3 of Printed Circuit Board Design Techniques for EMC Compliance, Second Edition

[nctnico]

The caps are 0805. Yes, I have CFGBVS are power 3.3V plane. I'm planning to connect the cap with via (minimum traces) to the plane and do the same with FPGA using microvia to the power plane.

No. Connect the capacitors to the plane and use 0402 sized capacitors; 0805 is way too big. The smaller a capacitor, the lower the internal inductance. Use 1uf 25V and 100nf 25V in a 3 to 1 ratio. Putting traces in series with a capacitor adds a huge amount of inductance; don't do that unless there is absolutely no alternative.

[AndyC_772]

https://cawteengineering.com/design-focus-parasitic-inductance/