The caps are 0805. Yes, I have CFGBVS are power 3.3V plane. I'm planning to connect the cap with via (minimum traces) to the plane and do the same with FPGA using microvia to the power plane.
Here is the answer. (connecting Cap to Planes)The wider the trace, the lower the inductance. The same goes for connecting component pads to planes. For each additional via (multiple vias in a pad), inductance will be reduced. The capacitance between the power and ground planes can also be very useful for decoupling when placed physically close together.
(connecting Component lead to cap) : Regardless of whether the PCB is simple or complex, almost all products require a trace to be present between a component lead and capacitor, or interconnect via. This interconnect trace, also identified as pin-escape, breakout, and similar terminology. A trace must be routed from the component to a via located nearby for connection to a signal, power, or ground plane. It is not possible, manufacturing wise, to have large vias embedded in a component's mounting pad. Solder may flow into the via, preventing the component from having a secure bond connection in addition to other manufacturing concerns
I got this from chapter 3 of Printed Circuit Board Design Techniques for EMC Compliance, Second Edition