RfC: Linux SBC using two layer PCB

[technix]

How do you think of that, a Linux-capable SBC with a two-layer PCB.

[Siwastaja]

I fail to see what purpose limiting yourself to a 2-layer PCB would serve, except to make design a bit harder and the product to perform a bit more poorly, likely.

It's very unlikely people would home-etch the boards, either. For that, you'd like to have large-pitch, low pin count devices, minimize number of vias, etc.

It can't be price difference, either, so what's the point? The end result looks exactly the same on the outside. Is there some extra appeal on owning a Ferrari but knowing it has a three-cylinder engine?

[SiliconWizard]

I'd be curious to see that.
Unless the RAM is embedded in the same SoC package, I don't know how you could seriously route like DDR(/2/3/4) RAM to a BGA SoC with only two layers.
If you still manage this (kudos), EMC is probably going to be piss-poor.

[technix]

It can't be price difference, either, so what's the point? The end result looks exactly the same on the outside. Is there some extra appeal on owning a Ferrari but knowing it has a three-cylinder engine?

It is price difference. Two-layer boards can be up to 5x cheaper than 4-layer at some facilities, for example JLCPCB. Also those usually have shorter turn-around time and better quality control.

Unless the RAM is embedded in the same SoC package, I don't know how you could seriously route like DDR(/2/3/4) RAM to a BGA SoC with only two layers.

The board I am currently making used a SiP with built-in RAM - Allwinner V3s. However I also do have a sketch where Allwinner A13 and its DDR3 SDRAM are done in two layers. In both cases the SoC are in QFP package.

When dealing with BGA SoC, I will have to increase layers. For example even though I will be using a memory module on my i.MX 6 chip, that is still a 6-layer board.

[Jeroen3]

I've linked it before somewhere here. But:
https://tibbo.com/store/plus1.html

I also got the Bananapi board running with Ubuntu 18.04. ^{*(ethernet doesn't stay online though)}
http://wiki.banana-pi.org/Banana_Pi_BPI-F2S

This chip could be done on 2 layer, if you really need to. Although 4 layer is probably better. But no need for more or dense memory routing.

[donotdespisethesnake]

How do you think of that, a Linux-capable SBC with a two-layer PCB.

Olimex made one using AllWinner chip, so definitely possible.

[technix]

I've linked it before somewhere here. But:
https://tibbo.com/store/plus1.html

That chip is unobtanium even on Taobao. Allwinner V3s is a similar business really though.

Do you consider F1C200S? QFP is way too large in many applications, and not everyone need a high speed Cortex A. Many people just need a small SoC that can run bare bone RTOS or a stripped down Linux with LCD driving capability. Essentially a cheap version of iMXRT.

I have considered that, but want to wait on linux-sunxi a bit for the u-boot and other drivers to fall in place first.


Here is my board, everything is packed into Raspberry Pi A+ physical size and a two-layer PCB:
* Allwinner V3s
* microSD card slot
* 64MiB SPI Flash (S25FL512S)
* RTC battery
* 10/100 Ethernet
* Wi-Fi + Bluetooth (AP6212)
* USB Type-A (actually OTG port)
* Audio line out
* Microphone
* USB power port (doubling as the debug serial port with onboard USB-serial chip HT42B534)

[Jeroen3]

It is a very new chip. Might be unobtainium for a while still.

That board looks very dense. But where is the memory?

[george.b]

You can run Linux on an AVR running an ARM emulator, so you could use even a single layer

For modern, high-speed stuff, a 2-layer PCB sounds like a bad idea.

[technix]

You can run Linux on an AVR running an ARM emulator, so you could use even a single layer

What I mean is something with a reasonable performance.

For modern, high-speed stuff, a 2-layer PCB sounds like a bad idea.

Well if the SoC somes with built-in SiP memory or PoP with memory riding on the back, and if the package involved is something that can easily fan out like QFP, QFN or shallow BGA, it is doable with two layers.

[OwO]

Normally I would say yes, you can do quite a lot on a 2 layer board, but with that layout the answer is NO. There is basically NO ground plane. Every signal on that board will couple into every other signal, and not through obvious paths either; because there is no ground, every chip's ground is basically floating, which means any signal that goes into any pin of the chip will induce voltage onto every other pin relative to chip ground. If you really want to get this to usable shape I say rip up all routing and take another look at component placement. Aim to place components so that almost nothing has to be routed on the bottom layer. All traces on the bottom must be no more than 1cm long; the bottom side must be a continuous ground plane with no slots longer than 1cm.

[george.b]

Well if the SoC somes with built-in SiP memory or PoP with memory riding on the back, and if the package involved is something that can easily fan out like QFP, QFN or shallow BGA, it is doable with two layers.

It's probably doable, yes. Like SiliconWizard said, though, you'll probably have poor EMC, and who knows what issues that could cause. Just because you can do something, doesn't mean you should, IMO. Especially without a ground plane.

But don't let that stop you, if you're really determined to do it. Who knows, you could prove us wrong.

[thinkfat]

I've seen the Octavo Systems OSD3358-SM being wired dead bug-style with just a few power rails connected. So why do a PCB at all? You can certainly pull the wires you need over to a breadboard and go from there.

If the lure is cheap JLCPCB prototype boards, rest assured that those are of only the lowest quality and quality control is at the "minimum we can get away with" level. You certainly won't go into any kind of volume production with them.

If you think of hobbyists ordering boards and building one of those themselves, you're kidding yourself.

[technix]

Normally I would say yes, you can do quite a lot on a 2 layer board, but with that layout the answer is NO.

Even worse when you have on board WiFi.

Something have to give when the sum of the courtyard areas of all the components involved is larger than the board area.

I've seen the Octavo Systems OSD3358-SM being wired dead bug-style with just a few power rails connected. So why do a PCB at all? You can certainly pull the wires you need over to a breadboard and go from there.

That is yet another unobtainium chip. Also AFAIK Octavo chips has internal PMIC, so as long as the wires can hold the current the core is correctly powered and power sequenced even when there is just one power pin connected. V3s is not such a chip, I have to power it properly.

If the lure is cheap JLCPCB prototype boards, rest assured that those are of only the lowest quality and quality control is at the "minimum we can get away with" level. You certainly won't go into any kind of volume production with them.

There are ways to force JLCPCB to put more attention into your quality without paying extra: for example have the PCB design pushing against their spec limits. They can not deliver failing boards, so such a challenging specs will force them to take it seriously. This is a 5mil trace board with 0.3mm vias, something that is right up there against their limits for a double layer PCB. They can and did complain, but they did advertise that level of specs and they have to stand up to it.

[technix]

I wonder how many of you both have a Chinese mobile phone account and reads Chinese. Currently at JLCPCB it is 10x to 40x more expensive to make a four layer board then making a 2-layer board of the same size, for Chinese users that is.

[langwadt]

I wonder how many of you both have a Chinese mobile phone account and reads Chinese. Currently at JLCPCB it is 10x to 40x more expensive to make a four layer board then making a 2-layer board of the same size, for Chinese users that is.

so it goes from dirt cheap to practically free?

[technix]

I wonder how many of you both have a Chinese mobile phone account and reads Chinese. Currently at JLCPCB it is 10x to 40x more expensive to make a four layer board then making a 2-layer board of the same size, for Chinese users that is.

so it goes from dirt cheap to practically free?

4-layer has always been CNY 200. 2-layer is currently CNY 5 for the first two orders of each month and CNY 20 for the rest of the month. This is 5 pieces of 10cm by 10cm boards, anything smaller wouldn't change the price much. (4-layer does have a 5cm by 5cm tier at CNY 100, but that size is too constraining.)

There are domestic competition going on.

[OwO]

This is what a reasonable 2 layer layout might look like:

There are a lot wrong with this design (bad footprints; via in pad) because it is an old design from when I first started out, but notice that all important traces go over an unbroken ground plane and all chips have local decoupling under the board.  This particular board required a few jumper wires because some signals couldn't be routed.
If this is to be a commercial product, don't do it unless there is extreme price pressure. The unit cost of a 4 layer board in volume is usually a small fraction of the total BOM cost, and cost savings of going to 2 layers is partly canceled by needing a bigger board.

[technix]

If this is to be a commercial product, don't do it unless there is extreme price pressure. The unit cost of a 4 layer board in volume is usually a small fraction of the total BOM cost, and cost savings of going to 2 layers is partly canceled by needing a bigger board.

For me that board is not intended to be a commercial product but a learning experience, so I am definitely putting cost on the front seat. What I want here is something that can work in a lab environment so I know what works and what does not next time when an actual commercial project comes. Think of me building up my reference design library and throwing a bunch of them in one test project to check if they works or not.

Specifically, this board contains:
* V3s core design with MP2122 and XC6206 as PMIC, powered from a single 3.3V rail.
* AP6202 Wi-Fi and Bluetooth, with control pins and interrupt pins combined into one I2C GPIO expander MCP23008.
* Software support for V3s, especially SPI booting and initializing Ethernet MAC address from 24AA02E48 in boot time.
* Device tree voodoo with Linux and u-boot.

As of price pressure, here in China designers are supposed to shave every possible cent off the BOM.

[technix]

I am not going to re-do the whole board since it is just a bunch of designs blocks mashed together as a verification board, however in order to address the ground issue I have increased via stitching. This board is intended to be cheap first, and I only expect it to work in a lab environment long enough so I can verify that I don't have major issues in those design blocks. Premature optimization is a bad thing, optimizing a bunch of unverified blocks is a sin.

[MarkL]

Here's another example of a 2-layer Linux board.  It can be done:

  https://www.eevblog.com/forum/projects/design-challenge-idea-linux-capable-sbc-without-bga/msg1119169/#msg1119169

The board works fine and has a decent ground plane.  However, it never made it out of prototype, and so never had any formal EMC testing done on it.

It was rather difficult to layout, and the time spent was not worth what it would have saved to simply go with more layers.

[GeorgeOfTheJungle]

This board is intended to be cheap first

But, how cheap? Because there are hundreds of tiny Linux SBCs and many are very cheap under $10 already. The "Chip", the RPi Zero, The OrangePi Zero, the NanoPi Zero, the Lichee Nano, the Banana Pis, etc etc.

http://linuxgizmos.com/ringing-in-the-new-year-with-136-open-spec-linux-sbcs-under-200/
https://www.friendlyarm.com/index.php?route=product/category&path=69&sort=p.price&order=ASC
https://www.seeedstudio.com/Sipeed-Lichee-Nano-Linux-Development-Board-16M-Flash-WiFi-Version-p-2893.html
https://www.seeedstudio.com/LicheePi-Nano-ARM926EJS-SoC-Development-Board-16M-Flash-p-2892.html

[technix]

But, how cheap? Because there are hundreds of tiny Linux SBCs and many are very cheap under $10 already. The "Chip", the RPi Zero, The OrangePi Zero, the NanoPi Zero, the Lichee Nano, the Banana Pis, etc etc.

Being a bunch of PoC's thrown together, there is no point spending a cent above bare minimum. It is a design challenge (think school assignment) and a functional verification board anyway.

It was rather difficult to layout, and the time spent was not worth what it would have saved to simply go with more layers.

Mine was difficult too, especially due to all the density (otherwise I would have a decent ground plane.)

Hmm maybe I should start designing up some function block modules? For example there is a standard M.2 pinout definition that matches the AP6212 Wi-Fi + BT block, so maybe I should design and build a M.2 module with just that block, and in future boards when such a function is needed I just put a M.2 2230 socket in there?

[Siwastaja]

Note you may be able to squeeze the design to smaller area on 4-layers, making the PCB cost difference somewhat smaller.
For example, a tightly packed, miniatyrized 50x100mm 4L design might become 60x120mm on 2L due to added ground and power traces which need to be done 100% on the component layers, preventing component placement.

Cost difference of bare PCB being 5x cheaper is of little importance, if the PCB is like 5-10% of the total cost. (Besides, I think you won't reliably find a 5x price difference, unless you deliberately shop for some special discount 2L and compare it to standard 4L.)

For a quick approximation, the PCBWay calculator shows $0.85/pcs for a 4L 50x100mm, and $0.65/pcs for a 2L 60x120mm, @ 1000pcs. I would be happy to pay $0.20 extra for shorter and less painful PCB routing time, smaller final product, and better EMI performance.

I would guesstimate your component BOM would be around $10 at minimum, and the assembly cost, which would be the same for 2L or 4L PCB, would be somewhere around $1 PCB.

Yes, you may be able to find a somewhat better deal on a 2L board, but you might find a good deal on 4L, as well.

If this is just for a design challenge, then I understand.

[technix]

Cost difference of bare PCB being 5x cheaper is of little importance, if the PCB is like 5-10% of the total cost. (Besides, I think you won't reliably find a 5x price difference, unless you deliberately shop for some special discount 2L and compare it to standard 4L.)

I'm talking 10x to 40x for me. That is beyond significant.

If this is just for a design challenge, then I understand.

This board is not quite a design challenge actually, more like a bunch of PoC's being thrown in together so I can verify the functional correctness of each module. I don't mind slowing the external circuitry down on this board really.