Author Topic: Open source CSI-2 Rx core for Xilinx FPGAs  (Read 10371 times)

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Offline malkauns

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Re: Open source CSI-2 Rx core for Xilinx FPGAs
« Reply #25 on: July 04, 2017, 05:32:11 am »
Thanks for your insights cirthix and Dave.  The fact that i'm getting an image such as the one below is very encouraging despite my horrendous setup.  From the look of the Firefly OV13850 board, I'm leaning toward making my own version that will connect directly to the Zybo board as suggested in cirthix's pic.  Upon looking at this board I see that there are 10 components (resistors/logic level converter?) on the front and 8 capacitors on the back.  As there are 10 on the front I'm guessing that they each sit between the MIPI data (8 pins) and clock pins (2 pins).  The capacitors are probably set up similar to my home made power board that you guys see in the pic.  Do you think that this is correct?  If so, what exactly are the 10 components that sit on the front of the board?

« Last Edit: July 04, 2017, 05:40:23 am by malkauns »
 

Offline daveshah

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Re: Open source CSI-2 Rx core for Xilinx FPGAs
« Reply #26 on: July 04, 2017, 07:07:29 am »
I believe the 10 resistors in the MIPI lines are 0 ohm resistors, presumably for test or because they weren't sure if they needed some resistance for some reason. I wouldn't bother with them personally, and just connect the MIPI straight through. The capacitors will be for local decoupling, probably 1 or 10 uF.
 

Offline malkauns

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Re: Open source CSI-2 Rx core for Xilinx FPGAs
« Reply #27 on: July 04, 2017, 07:16:20 am »
what do you mean by "local decoupling" ?
 

Online Berni

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Re: Open source CSI-2 Rx core for Xilinx FPGAs
« Reply #28 on: July 04, 2017, 07:38:32 am »
I been working with MIPI-DSI on the Lattice and i found signal integrity to be pretty important.

My MIPI bus was running at 600Mbit over a single lane there so pretty quick, but there are even faster MIPI buses out there. I was running it over ribbon cable with the differential pairs next to each other and there are cases where touching large areas of the cable could cause glitches in the image. Terminating the lines correctly made it more resilient. Touching just one of the pairs with a scope probe breaks it completely. I had to use a differential active probe to get a good look at it without mangling up the waveform (And used a 4GHz scope)

So do take lots of care with the wiring for the MIPI pairs. I am surprised it worked at all with your wire ratsnest setup.

The way to go is to try maintaining a differential transmission line for as long as possible. the FPC cable is a reasonable transmission line with the pins next to each other and so rounded by ground in the pinout. Then you want to use twisted pair to wire to your FPGA board. Most FPGA dev boards have some pins on the header that are routed deferentially to the FPGA, its easy to spot them on the PCB layout, use those if possible. Also one ground is not enough, use 3 or 4 ground wires to make sure you have a low inductance connection. For power i would not be worried too much, as long as you have a capacitor close to the camera connector.
 

Offline alga_kbk

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Re: Open source CSI-2 Rx core for Xilinx FPGAs
« Reply #29 on: June 02, 2018, 05:50:30 am »
Hi there!

Thanks, Dave for your source codeshare!

I'm new in image processing sorry if I bore you. I'm also trying to set up is the project with the OV13850 and have the question, on I2C is there a way to obtain the response of camera?  In order to be sure that camera is working. As you all mentioned before about signal integrity, I haven't already made breakout board for connection just using the cable for connection and didn't obtain anything on MIPI bus
 

Offline daveshah

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Re: Open source CSI-2 Rx core for Xilinx FPGAs
« Reply #30 on: June 02, 2018, 07:58:57 am »
I don't implement such a thing in my simple I2C core, but you could put something like a soft processor with a I2C core in to implement that and do further testing.

The code as is will run at a line rate of about 1Gbps/lane, this will almost certainly not work using anything other than a PCB. Can you post a photo of your setup?
 

Offline alga_kbk

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Re: Open source CSI-2 Rx core for Xilinx FPGAs
« Reply #31 on: June 04, 2018, 04:39:49 am »
Hi Dave!

Thanks for your help! Sure will attach the setup photo later. As I understand on I2C there is a response from the camera after every message that it obtained, will try to play with that. I wanted to know, is there any way to decrease the MIPI line rate to 100Mbps/lane?
« Last Edit: June 04, 2018, 04:42:18 am by alga_kbk »
 

Offline daveshah

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Re: Open source CSI-2 Rx core for Xilinx FPGAs
« Reply #32 on: June 04, 2018, 08:10:32 am »
Hi alga!

It's a long time since I've touched the config for an Omnivision camera, but it should be possible to reduce the line rate considerably. The first thing to try is to reduce the input clock (MCLK) to the camera, it should be possible to reduce that by at least a factor of two. Beyond that you'll probably have to play with the PLL and D-PHY settings. Maybe have a look at existing configs in Linux kernel drivers for your camera?

Which camera module are using again?
 

Offline alga_kbk

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Re: Open source CSI-2 Rx core for Xilinx FPGAs
« Reply #33 on: June 05, 2018, 04:38:29 am »
Hi Dave!

Thank you very much, today will play with it. I'm using  OV13850 camera from Firefly RK3288 module.
 


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