Electronics > FPGA

Help Please: (Virtual) JTAG Interface - data transmission

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SparkyNZ:
Can somebody please help me - I am trying to understand how data is transmitted using the vJTAG component on my FPGA. Sorry I have no idea which sub forum category this belongs in - it's not really an FPGA question.

I have this logic analyzer screenshot.



Using TCL script, I am transmitting the value 6 in decimal (0110 in binary,  00000000 00000000 00000000 00000110 in 32 bits.. or perhaps 011000000 00000000 00000000 00000000 depending whether big/little endian is used)

Can anyone marry up where the 32 bits actually are in this image?

My understand was that the bits appear on the tdi signal.. sdr would indicate data is available and should be shifted into a register and udr would indicate that data is available (shifting of data into register is complete). And I'm also working on the assumption that the tck signal is the clock.

What I find confusing is that tck doesn't appear to be a regular clock.

I would have thought that the bump in tdi after my red marker are the two 11 bits in the 0110 part of the transmission - but how on earth could that be considered 2 bits of data when tck is not oscillating during that period?

migry:
Hmm , perhaps I need glasses, but I don't see TMS.

TMS moves between the 16 states of the TAP state machine. I need to see this to see where the instruction register is loaded and where the data register is loaded.

JTAG is actually quite a simple serial format, and there is plenty of data available online to interpret the waveforms.

Once a register has been selected, it is a simple serial format with data on TDI clocked in on the rising edge of TCK, the register being a simple serial shift register. The output of the register appears on TDO on the negative edge of the clock.

A very very simple rule of thumb is to look for a long sequence of TCK where TMS is low, this indicates when the register is being serially loaded/unloaded. There is normally one or two cycles(clocks) of TMS high at the end of the serial load. User registers can be little or big endian, whereas the endianess of the instruction register is defined (but I forget which). In your case you are looking for 31 (32 minus one) rising edges of TCK where TMS is low.

SparkyNZ:
Sorry I have just this minute pulled all of the logic analyzer wires out - so no TMS signal I'm afraid. My FPGA is getting the correct data. I was just trying to make some sense of it all visually - I had another problem and that was that I was only looking at the UDR signal on a TCK positive edge. Of course UDR and TCK go high around the same time so I was missing the UDR transition sometimes.

Does that TCK look normal to you?? I saw a lovely Modelsim diagram in Intel's Virtual JTAG User Guide for (DR Shift Waveform, see below) and it has a perfect clock showing or TCK - continuous with a 50/50 duty cycle.



I just decided that my logic analyzer perhaps isn't fast enough to keep up with the TCK clock.

migry:
Apologies. This is my first visit to the forum for some time.

At first glance something doesn't look right with TCK. In my experience of this signal, the off-state is normally '0'.

Reason is: data is shifted into the selected data register on the RISING edge of TCK; and data  is shifted out of TDO on the falling edge of TCK. SO to shift one data bit in and get a corresponding one out you need TCK to go low to high and then back low again.

That's not to say that you can't make it work using an off-state of '1', but for me it doesn't match my experience of this protocol.

Assuming that you are starting in the state Run-Test-Idle (the normal state in which the state machine is "parked" when not active) 2 rising edges of TCK with TMS high takes us to Select-IR-Scan, where we are about to load the instruction register. This happens where TMS is low and the final shift when TMS goes high again. There are 3 rising edges of TCK with TMS high, which is where we move out of Shift-IR to Exit1-IR then Update-IR and then to Select-DR-Scan. TDI is low during the instruction load. My vague recollection is that an all 0's instruction has a special meaning, but I forget. Google reminds me that all 1's is the BYPASS instruction. Some example BSDL files I just looked at assign all 0's to EXTEST (i.e. the instruction to access the boundary scan chain), but I can't recall is this is a rule or not.

You then load 4 data bits into the selected register where TMS is 0-0-0-1 and I see TDI is 0-0-1-1 which ties in with your bottom trace.

The final rising edges of TCK sample TMS as '1' and this forces the state machine to the reset state Test-Logic-Reset.

I don't know if this is helpful. Might be best to DM me if you have any specific JTAG questions as I should then get an email alert.

NorthGuy:
Read the JTAG specification. It explains everything.

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