FPGA

ACTEL Activator 2S - APSW software needed

Serializing: shift registers vs. multiplexers

Comparing performance of genuine vs cloned programmers for Intel/Altera FPGAs

VERILOG: Equality test with don't cares

Help with Altera Cyclone III configuration problems.

MUXes or tristate for busses?

OpenCores.org login

AMD/Xilinx releases Microblaze V softcore

FOR SALE: Altera Terasic DE1 Development Board Kit

New generateur DDS with Altera cyclone IV.

Are latches always bad?

Xilinx Announces Vitis

Xilinx clocking wizard - Requested frequency vs actual frequency

VHDL add and divide

EBAZ4205 questions / problem

No more Xilinx CPLDs and Spartan 3s

A 5V CPLD in 2023?

Wrong voltage DDR3 chip on Arty A7 board?

Avnet for Xilinx XC3S400A

5-stage pipelined CPU and synchronous memory access

Should I use an FPGA for this project?

#Rant: Intel can't even host files correctly.

How exactly does differential signal lead to low power consumption in FPGAs?

Cordic on verilog

XC9500XL : using "Timing driven" macrocells power setting

Suggestions for a dev board for learning some FPGA things

Partial reconfiguration of FPGA on the fly

« 1 2  All »

DDR3 Refresh and Micron DDR3 model

Xilinx's "Device Lookup" Service

NCO to generate square wave

Values of signals AT the rising/falling edge

PALCE Chips

FPGA/CPLDs that are hand solderable

State machine design choice

Question about MAX7000 CPLDs

Verilog: Adding "slices" of numbers

Quick checking for VHDL syntax

ATF1502 programming & 'wrong' id (fake?)

Quartus 19.1 on Ubuntu 18.04 problems with internet and usbblaster

Reading contents of Altera PLD