FPGA

DDR3 Data capture using ISERDESE2

TVS diodes in FPGA development boards

timed state machines VHDL

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Anyone else misses jtag_loader?

LPDDR4 memories

A 5V CPLD in 2023?

Basys 3 Pmod Tips

Best FPGA for the job - low-speed LVDS deserializer

Should I use one big always block or several smaller ones?

Reset in Verilog isn't working as planned

Elegant way to select output type from a register or wire ?

And the warning is gone ... Simple DivClk by N

How to add in Verilog? Quartus, EPM7064STC44 etc.

Re-enabling JTAG in Altera Max3000A PLDs

Gowin: Which programmer to use?

Using embedded I2C in Lattice MachXO2 as DS3231

New Verilog: Incrementing without getting continous assignment conflict

Zynq Quad SPI controller: has anyone used it successfully for non-flash devices?

Disciplined signal clock to PPS

Loading FPGA configuaration from SPI flash

Trouble shooting ZCU111 RFSoC board

Simultaneous read/write with Quartus-|| single clock FIFOs

Interfacing peripherals that run on different clocks.

Terasic DE5-NET

Ideas on what type of JTAG device to purchase

Gowin triple speed ethernet MAC. Trouble with tx data

Need driver for XUPV2P board

Efinix Trion FPGA's

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Quartus ALTFP_SQRT IP not working in simulation

Alternative for Lattice 4032ZE?

Xilinx: interface microblaze to hard IP

USB3320 Device not able to detect with Zynq RFSoC

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Cyclone IV PLL not working correctly

Partial reconfiguration of FPGA on the fly

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Sorting out 'Unbuffered IO' warnings for Lattice ICE40 Ultralite devices

del

Lattice CrossLink NX EVB Clocking w/higher speed clocks

Help with Verilog vectors

Virtex-6 Partial reconfiguration

EP2C5/EP2C8 Mini Board