FPGA

Altera EPM3064 CPLDs suck - but why? Maybe I got a lot of garbagge ones...

Why cant I add a 5th state to my state machine?

VHDL - Why is my testbench signal "X" (= bus conflict)?

No more Xilinx CPLDs and Spartan 3s

FPGA based Direct Digital Synthesis

Altera MAX 10 external memory?

Embedded Graphics Interface GUI

Innovate FPGA Design Contest

Xilinx ISE 14.7 to support windows 10 by the end of the year (time machine...)

Multiported RAMs [SOLVED]

Lattice Diamond v 3.11 on Linux: problem with ftdio_sio

Tang Nano 1K (Gowin FPGA) VGA output - artefacts, sync problem

Xilinx Zynq 7000 Sample Request

How to feed an int to a third party module which wants a parameter in "Quotes"?

Sine Wave on FPGA

Should I use an FPGA for this project?

RAM timing problems (SOLVED)

Verilog: Adding "slices" of numbers

Why does my macrocell count increase?

FPGA recommandations for education

Programming ICE40 FPGA on a board?

Low input frequency (1MHz) multiplication via PLL

Max10 JTAG header ???

Altera configuration Flash - crazy prices - alternatives?

Arithmetic operation caches

Poor man's FPGA DAC

Exploring an old FPGA and software (Altera Cyclone with Quartus-II 10.1)

Quartus Prime 18.1 Can't fit design in device

Ring Oscillator on an fpga

FPGA/CPLDs that are hand solderable

cheap fpga recommendation

Optimizing MUXes

New Efinix FPGA family - Topaz

Very simple FPGA for ADC 12-bit

Pruning bits in digital downconverter (DDC)

Values of signals AT the rising/falling edge

Xilinx Kria SoMs

Fast ADC interface with FPGA

How exactly does differential signal lead to low power consumption in FPGAs?

Question about MAX7000 CPLDs