FPGA

FPGA application examples

« 1 2  All »

Lattice ICE40 instantiating RGB/IR pins as regular user IOs.

Lattice Diamond with Synpify Pro - cannot specify a clock

Lattice Mach XO2 - Unable to simulate reading TraceID through Wishbone

Exercise-focused FPGA learning resource?

CPLD divide by 1.5 50% duty cycle

Lattice Mach XO2 - Reading UFM flash

Implementing D-type latch with ATF16V8CZ

Advice on an imaging project

Xilinx Ise 14.7 create an ucf file pinout

Intel\Altera EP53F8QI Short to GND Fault

How to config the AD9517-3 registers(fine delay ) to produced 180-degrees output

2019, the best way to learn CPU on FPGA

« 1 2 3 4  All »

Should a new EPM3064A be 'blank'?

RISC-V SOC on an ICE FPGA: what peripherals are available?

internal clock divider in FPGA

Lattice XP2 DCS issues

FPGA Clock (setup slack) issues.

« 1 2 3  All »

problem with LVDS Oscillator on Zynq borad !!!!!!!

Noise in DDR FPGA implementation

I2S clock from 100MHz on Artix-7

Tthe VDF Alliance FPGA Competition.

Error In Encoder (Verilog Code)

Help with this verilog video

Commenting verilog code - best practice?

Quartus programmer chain file [Solved]

Selecting pin impedance on fpga

input [7:0] data; in verilog. Serial or parallel?

Very simple FPGA for ADC 12-bit

case statement written so output is low, but sim shows high pulse?

Going to learn FPGA, seeking advice about choosing dev. board etc.

« 1 2 3  All »

Cheap in-system FGPA programming

« 1 2  All »

CPLDs - which one to start with

Are Xilinx XC7A35T actually the same die as something else or...?

« 1 2  All »

VHDL add and divide

Debouncing technique for a SPDT switch connected to CPLD

Anyone try repeating this guys genetically evolving FPGA experiment?

« 1 2  All »

FPGA Algorithm Projects

asynchronous reset mechanism of D flip-flop in yosys

« 1 2 3  All »

Xilinx is now available at Mouser!