FPGA

First FPGA?

How to change slew rate in quartus pin planner?

FPGA "soft" serializer

Lattice ispLever

generating arbitrary waveforms with zynq 7000 series

Lattice iCECube2 E2055 Error while doing placement of the design

Beginner Altera DE1-SoC Audio Equalizer

Simple Fade Counter as a tool for get students skills

What am I doing wrong?

Fast Arbiters for On-Chip Network Switches

XC9500XL slow clock

Quartus Prime (Time Quest) Difficulty Generating Report

Lattice iCE 40 FPGA distorted clock signal

Getting started Altera Flex 10K questions from FPGA newby

Here is something I built for my own enjoyment.

A3PN060 & Libero IDE

Intel Quartus Prime Pro - How is Modelsim-Altera supposted to work?

Any Interesting Projects For Zynq

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Should i care about AXI4 for my project ?

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Beginner's CPLD Development Board Advice ?

Audio DSP algorithms

Implementing Carry Look Ahead Adder

Programming a .mcs flash file to Spartan 6 FPGA using Bus Pirate

Active-HDL 10.5 - VHDL assignment woes

Detect Protocol on bus

Unbricking a Digilent CMOD A7 FPGA devboard.

Verifying RISC-V compliance

Tools for programming 16V8 GAL

Advice for Altera Beginner

Cheapest FPGA supporting 450MHz SERDES for ADC interfacing

Undergraduate thesis and FPGA

A new kid in the block

How to program 82S100 devices

Determine whether a binary number is of power of two in verilog code

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Unspecified I/O standard in vivado when trying to set AXI gpio to 1 bit width

Max10 JTAG header ???

10 level logic in VHDL (for simulation only)

FPGA application examples

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Lattice ICE40 instantiating RGB/IR pins as regular user IOs.

Lattice Diamond with Synpify Pro - cannot specify a clock