FPGA

Altera configuration Flash - crazy prices - alternatives?

Exploring an old FPGA and software (Altera Cyclone with Quartus-II 10.1)

Why does my macrocell count increase?

RAM timing problems (SOLVED)

Microsemi/Microchip Polarfire tools . what are they like ?

Question about MAX7000 CPLDs

Developer runs Doom on Altera CycloneV

Video pass-through Xilinx based device, general thoughts/queries

Pruning bits in digital downconverter (DDC)

Analog video output with FPGA ?

How exactly does differential signal lead to low power consumption in FPGAs?

Xilinx Kria SoMs

issues with synthesis and implementation of quad SPI flash controller

Values of signals AT the rising/falling edge

Fast ADC interface with FPGA

First FPGA PCB - JTAG Unable to Scan Device Chain

Very simple FPGA for ADC 12-bit

NCO to generate square wave

Cheapest FPGA supporting 450MHz SERDES for ADC interfacing

Mixing DDR3 data lines between bytes

GOWIN FPGAs

FPGA failure modes

Learning clock domain transitions on FPGAs (Xilinx)

Warnings and FPGA design

Derived clocks, best practices?

MUXes or tristate for busses?

[Closed:Faulty] Clock works intermittently - Cyclone IV board from Aliexpress

Forcing usage of clock enable in MAX7000 CPLDs

Lattice Certus-NX PCIe, or alternative

RISC-V SOC on an ICE FPGA: what peripherals are available?

FPGA design: bus size vs die size

Verilog equivalent of a variable?

Vivado for Windows, what do I need

FPGA USB3.0 Mass Storage mode?

Need a really dumb PC/Win RS232 terminal program.

Xilinx Announces Vitis

OpenHBMC. Open-source AXI4-based HyperBus memory controller

Which HDMI serializer chip to use for small fpga design?

Gowin: Which programmer to use?

Documenting digital designs for FPGAs