FPGA
Topics
[2] asynchronous reset mechanism of D flip-flop in yosys
[3] Xilinx is now available at Mouser!
[4] Register power consumption on FPGAs
[5] Some thoughts on AXI pipe handshake protocol and timing closure
[7] Vivado is shit at timing optimization?
[8] Verilog module with SPI needs to read AXI
[9] Fractional-N frequency synthesis does not work on Mach XO2 FPGA
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