FPGA

Confused: Can FPGA measure less than 0.1ns delay between digital pulses?

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Xilinx ISE Ceil and Floor Can't Synthesize But Can Simulate?

Universal JTAG adapter?

Chiptunes! A Dual YM2149 PSG Audio core for BoxLambda.

DDR3 Refresh and Micron DDR3 model

Devices containing repurposable FPGAs

Program Cyclone IV with USB blaster from arm64 linux

CYCLONE V HPS - ACCESS SDRAM CONTROLLER SUBSYSTEM OVER JTAG WITH OPENOCD

IBIS model for DDR4 memory

Weird effect on Cyclone V + HPS after soft or hard boot

Verilog generate and buses

Documenting digital designs for FPGAs

Interfacing AD9625 with FPGA

Cannot get data from BRAM IP

Cheap FPGA for HDMI 2.0 4k reception?

How to pipeline DSP48 input?

Zynq Based Digital Camera Design Help (issues with Zynq)

VCD file identifier length

Selection and general know how of building an Arcade ROM board emulator (FPGA)

Attempting to identify mysterious PAL Hardware Description Language

Lattice iCECube Licensing key

Which USB Blaster for Altera Max 10 ?

VHDL assigning to and from array gives "XXXX"

Zynq DMA Scatter Gather still included when disabled...?

FPGA bargain on Ebay

help on choice programmer JTAG

Microblaze 64 bit

Faster FPGA compilation times using... FPGA? GPU?

Why wide demux allows the partitioning of memory bandwidth to be able to change

Mixing DDR3 data lines between bytes

UART rx is not properly working

Cordic on verilog

Intel to spin off FPGA biz

BGA Confusion

PMIC for Z7020

why I get BAD PACKET ERROR?

inout with physical pins in Verilog

Planning/design/review for a 6-layer Xilinx Artix-7 board for DIY computer.

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FPGA Nexys A7 100T Board with PMOD ESP32

VHDL exponential operator (**) works for synthesis?