FPGA

Gowin: JTAG device detection failure (pretty scope pictures included!)

Vivado for Windows, what do I need

Xilinx Announces Vitis

Some thoughts on PCI on 3.3V FPGAs

Divide/Mod a 32-bit value by 1000.

How to evaluate as a Beginner how much will fit in a certain amount of LUTs?

Reading contents of Altera PLD

GateMate - An European FPGA

Your choice for <$3 FPGA/CPLD with >50 IO, >200 LUT4?

FPGA "soft" serializer

Is here any speed difference in MidRange FPGAs from different manufacturers ?

Xilinx Spartan 3A availability

Beginner's CPLD Development Board Advice ?

Intel to spin off FPGA biz

AMD/Xilinx releases Microblaze V softcore

Altera FLEX 8000: Extracting "bitstream" from .sof file?

The cheapest FPGA+MCU integration in one chip I ve ever seen in China

Intel/Altera - DDR3 megafunction fails in Quartus 20.1.1

Parameters and generate

VHDL Code to Verilog Code

Understanding FPGA timing optimisation

The Blair Witch story of my first FPGA devboard made from a printer front panel

Correctly handling clocks on a older Cyclone IV

FPGA SDR Training - Dev boards

Who's working with Symbiflow, Migen, Litex, Risc-V and the like?

5-stage pipelined CPU and synchronous memory access

FPGA Design Security, Without Limiting Modification

True HDMI for Tang Nano 9K

Lattice FPGA programmer

Power Consumption of Cyclone IV on each voltage rail

usb verilog softcore questions

Hyperram to MAX10 (with no DQS shift)

Typical use cases for massive FPGA's?

Altera USB Blaster works only once

Capturing ADC Data using LVDS interface

Simple Fade Counter as a tool for get students skills

Which USB Blaster for Altera Max 10 ?

ICE40 Board Design review

CPLDs - which one to start with

Variable clock divider