FPGA

Teaching FPGA from/to home ?

FPGA under $10 ?

Help required in Library of Zyn 7010 by xilinx SoC

XC9500XL : using "Timing driven" macrocells power setting

XC9500XL : using a GCK pin as regular IO to match long transition time clock

Microcontroller simulation using Xilinx FPGA

JESD204B over fiber

Can anyone program a PLS153 or a 82S153 from a good part/

Digital Oscilloscope Design with FPGA

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FPGA USB3.0 Mass Storage mode?

If Lattice iCE40UltraPlus has DDR primitives like ODDR in Xilinx?

Indexed pins in constraints file?

Intel\Altera EP53F8QI Short to GND Fault

Video pass-through Xilinx based device, general thoughts/queries

MUXes or tristate for busses?

Xilinx ISE 14.7 - IMPACT is a disaster

AHB-Lite Crossbar

5-stage pipelined CPU and synchronous memory access

Serializing: shift registers vs. multiplexers

Efinix

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Combinatorial inside or outside of a process

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Example of using Xilinx memory interface?

Partial reconfiguration of FPGA on the fly

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Using ULPI USB PHYs for custom data links

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Arithmetic operation caches

GOWIN FPGAs

PLLs or otherwise clock management blocks with clock enables

Memory caches and large block copy

Lattice ECP5: opinion?

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Saturating counters

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Looking For ViewDraw

Zynq board throws "pl35x_nand_cmd_function timed out" error

Ft2232h fifo realtime data stream

CPLD stepper motor AN488

Hacking surplus Pano Logic thin clients

am I the only one who thinks Vivado/Vitis is a muddled mess?

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Anyone played with these cheap ($50) Zynq boards

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Easy way to see number of registers along datapath in Vivado?

2nd Order Sigma-Delta Digital to Analogue Converter (SD-DAC) in Verilog

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Switching read & write between memory banks with a flag (verilog) - timing issue