FPGA

VHDL exponential operator (**) works for synthesis?

Issues with git cloning repo with "RISC-V RV32IMC Toolchain"

How to describe a 74HC74 as part of a Spartan-6

FPGA Question.....

Successfully constraining paths in (old) Quartus

Pmod BLE Module with MCU

FPGA Bluetooth Project

NEORV32 soft-core CPU (RISC-V) - bootloader is not working

xilinx Z7 (7Z045) control chip warms up quickly at boot time

Has somebody tried TCL scripts with "Gowin EDA" (Gowin FPGA Designer)

AMD/Xilinx announced their own RISC-V soft-core

« 1 2  All »

NEORV32 (RISC-V) soft-core "coremark" result

ATF15XX Dev DK2 example file PLDs etc

Low budget FPGA needed

« 1 2 3 4  All »

Port pins missing in Debug net list

No pulse in CLK test points

Quick checking for VHDL syntax

Replacing a Color Prom on a Donkey Kong Jr Arcade with a GAL22v10

PALCE Chips

Need decode the 8B10B data sequence of 1.3Gbps speed within Lattice FPGA LFE-5UM

Vitis 2023.1 would fail to compile when I add a custom IP

Need help writing to XDMA

Suggestions for a dev board for learning some FPGA things

Intel/Altera - DDR3 megafunction fails in Quartus 20.1.1

Renesas SLG46826 GreenPAK SPLD, what are the three memory regions used for?

GreenPAK SPLD blinky?

Two basic GreenPAK SLG46826 SPLD questions

Install Vivado on SD card (use NTFS)

CPLD/FPGA design flow

Tindie.com & Micro-Nova order frustration (it finally arrived!)

Being Stuck with Efinix

FPGA SPI Timer, help needed

VP1902

Need documentation for bittware XUP-VVP

ICE40 series questions, from a noob

Verilog Assign Logic to Wire Array?

Arcade game repair

MCU with FPGA vs. SoC FPGA

« 1 2 3 4 5 6 ... 8  All »

What the hell is up with Vitis HLS.

Pango Micro FPGAs?