FPGA

iCE40UP - how to select SPI Master config mode?

First design with FPGA, DDR4 and Hyperlynx SI simulation

Are GreenPack SPLDs logic prone to glitches?

Help finding a small and low cost programable logic IC.

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Pango Micro FPGAs?

What the hell is up with Vitis HLS.

MCU with FPGA vs. SoC FPGA

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Arcade game repair

Verilog Assign Logic to Wire Array?

ICE40 series questions, from a noob

Need documentation for bittware XUP-VVP

VP1902

FPGA SPI Timer, help needed

Being Stuck with Efinix

Tindie.com & Micro-Nova order frustration (it finally arrived!)

CPLD/FPGA design flow

Install Vivado on SD card (use NTFS)

Two basic GreenPAK SLG46826 SPLD questions

GreenPAK SPLD blinky?

Renesas SLG46826 GreenPAK SPLD, what are the three memory regions used for?

Intel/Altera - DDR3 megafunction fails in Quartus 20.1.1

Suggestions for a dev board for learning some FPGA things

Need help writing to XDMA

Vitis 2023.1 would fail to compile when I add a custom IP

Need decode the 8B10B data sequence of 1.3Gbps speed within Lattice FPGA LFE-5UM

PALCE Chips

Replacing a Color Prom on a Donkey Kong Jr Arcade with a GAL22v10

Quick checking for VHDL syntax

No pulse in CLK test points

Port pins missing in Debug net list

Low budget FPGA needed

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ATF15XX Dev DK2 example file PLDs etc

NEORV32 (RISC-V) soft-core "coremark" result

AMD/Xilinx announced their own RISC-V soft-core

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Has somebody tried TCL scripts with "Gowin EDA" (Gowin FPGA Designer)

xilinx Z7 (7Z045) control chip warms up quickly at boot time

NEORV32 soft-core CPU (RISC-V) - bootloader is not working

FPGA Bluetooth Project

Pmod BLE Module with MCU

Successfully constraining paths in (old) Quartus